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sinclairrf |
################################################################################
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#
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# Copyright 2012-2013, Sinclair R.F., Inc.
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#
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################################################################################
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import math
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import re
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from ssbccPeripheral import SSBCCperipheral
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from ssbccUtil import SSBCCException;
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class monitor_stack(SSBCCperipheral):
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"""
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Simulation-specific peripheral to flag invalid stack operations and display
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the execution history immediately before the invalid operation.\n
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Invalid data stack operations are:
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pushing onto a full data stack
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dropping from an empty data stack
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nipping from an almost empty data stack\n
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Invalid return stack operations are:
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pushing onto a full return stack
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dropping values from an empty return stack
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returns from a data entry on the return stack
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non-return operations from an address entry on the return stack\n
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Invalid data operations are:
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swap on an empty or almost empty data stack
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in-place operations on an empty or almost empty data stack\n
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Usage:
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PERIPHERAL monitor_stack \\
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[history==n]\n
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Where:
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history=n
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display the n most recent operations when a stack error is encountered
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Note: Normally the last 50 instructions are displayed.
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"""
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def __init__(self,peripheralFile,config,param_list,loc):
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# Use the externally provided file name for the peripheral
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self.peripheralFile = peripheralFile;
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# Get the parameters.
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for param in param_list:
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param_name = param_list[0];
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param_arg = param_list[1:];
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if param_name == 'history':
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self.AddAttr(config,param,param_arg,r'[1-9]\d*$',loc,int);
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else:
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raise SSBCCException('Unrecognized parameter at %s: %s' % (loc,param,));
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# Set optional parameters.
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if not hasattr(self,'history'):
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self.history = 50;
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# Configure the system for this peripheral.
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config.functions['display_trace'] = True;
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def GenVerilog(self,fp,config):
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body = self.LoadCore(self.peripheralFile,'.v');
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outport_pure_strobe = '';
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for ix in range(config.NOutports()):
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thisPort = config.outports[ix][2:];
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thisIsStrobe = True;
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for jx in range(len(thisPort)):
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signal = thisPort[jx];
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signalType = signal[2];
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if signalType == 'data':
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thisIsStrobe = False;
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elif signalType == 'strobe':
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pass;
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else:
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raise Exception('Program Bug: Unrecognized outport signal type "%s"' % signalType);
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if thisIsStrobe:
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if len(outport_pure_strobe) > 0:
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outport_pure_strobe += ' || ';
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outport_pure_strobe += ('(s_T == 8\'h%02X)' % ix);
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if len(outport_pure_strobe) == 0:
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outport_pure_strobe = '1\'b0';
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outport_pure_strobe = 'wire s__outport_pure_strobe = ' + outport_pure_strobe + ';';
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for subs in (
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(r'\\bix__', 'ix__monitor_stack__',),
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(r'\\bs__', 's__monitor_stack__',),
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(r'@CORENAME@', config.Get('outCoreName'),),
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(r'@HISTORY@', str(self.history),),
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(r'@LAST_INPORT@', '9\'h%03X' % config.NInports(),),
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(r'@LAST_OUTPORT@', '9\'h%03X' % config.NOutports(),),
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(r'@NINSTRUCTIONS@', str(config.Get('nInstructions')['length']),),
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(r'@OUTPORT_PURE_STROBE@', outport_pure_strobe,),
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):
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body = re.sub(subs[0],subs[1],body);
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for ixBank in range(4):
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memParam = config.GetMemoryByBank(ixBank);
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if memParam:
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maxLength = memParam['maxLength'];
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else:
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maxLength = 0;
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body = re.sub('@MEM_LIMIT_%d@' % ixBank, str(maxLength), body);
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fp.write(body);
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