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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [monitor_stack.v] - Blame information for rev 10

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1 2 sinclairrf 
//
2 
// monitor_stack peripheral
3 10 sinclairrf 
// Copyright 2013, Sinclair R.F., Inc.
4 2 sinclairrf 
//
5 
// Note: The validity of N and T are not monitored for invalid operations.  For
6 
//       example, if N is not valid and a "swap" is performed, then the data
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//       stack is no longer valid and an error is detected.  Thus, the validity
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//       of N and T do not need to be monitored for "swap" operations.
9 
generate
10 
reg s__PC_error = 1'b0;
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localparam L__INSTRUCTION_MAX = @NINSTRUCTIONS@-1;
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always @ (posedge i_clk)
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  if (~&L__INSTRUCTION_MAX[0+:C_PC_WIDTH] && (s_PC > L__INSTRUCTION_MAX[0+:C_PC_WIDTH])) begin
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    $display("%12d : PC passed instruction space in @CORENAME@", $time);
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    s__PC_error <= 1'b1;
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  end
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//
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reg s__N_valid;
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reg s__R_valid;
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reg s__T_valid;
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reg s__data_stack_valid;
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reg s__return_stack_valid;
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//
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initial s__T_valid = 1'b0;
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always @ (posedge i_clk)
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  if (i_rst)
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    s__T_valid <= 1'b0;
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  else case (s_bus_t)
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    C_BUS_T_OPCODE:     s__T_valid <= 1'b1;
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    C_BUS_T_N:          s__T_valid <= s__N_valid;
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    C_BUS_T_PRE:        case (s_opcode[0+:2])
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                          2'b00: s__T_valid <= s__T_valid;
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                          2'b01: s__T_valid <= s__R_valid;
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                          2'b10: s__T_valid <= s__N_valid;
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                          default : s__T_valid <= s__T_valid;
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                        endcase
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    C_BUS_T_LOGIC:      case (s_opcode[2])
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                          1'b0: s__T_valid <= s__T_valid;
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                          1'b1: s__T_valid <= s__N_valid;
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                          default : s__T_valid <= s__T_valid;
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                        endcase
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    default:            s__T_valid <= s__T_valid;
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  endcase
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//
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initial s__N_valid = 1'b0;
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always @ (posedge i_clk)
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  if (i_rst)
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    s__N_valid <= 1'b0;
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  else case (s_bus_n)
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    C_BUS_N_N:          s__N_valid <= s__N_valid;
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    C_BUS_N_STACK:      s__N_valid <= s__data_stack_valid;
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    C_BUS_N_T:          s__N_valid <= s__T_valid;
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    C_BUS_N_MEM:        s__N_valid <= 1'b1;
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    default:            s__N_valid <= s__N_valid;
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  endcase
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//
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initial s__data_stack_valid = 1'b0;
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always @ (posedge i_clk)
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  if (i_rst)
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    s__data_stack_valid <= 1'b0;
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  else if (s_stack == C_STACK_INC)
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    s__data_stack_valid <= s__N_valid;
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  else if ((s_stack == C_STACK_DEC) && (s_Np_stack_ptr == {(C_DATA_PTR_WIDTH){1'b0}}))
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    s__data_stack_valid <= 1'b0;
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  else
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    s__data_stack_valid <= s__data_stack_valid;
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//
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reg s__data_stack_error = 1'b0;
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@OUTPORT_PURE_STROBE@
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always @ (posedge i_clk)
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  if (!s__data_stack_error) begin
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    if ((s_stack == C_STACK_DEC) && !s__T_valid) begin
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      $display("%12d : Data stack underflow in @CORENAME@", $time);
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      s__data_stack_error <= 1'b1;
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    end
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    if ((s_stack == C_STACK_INC) && (s_Np_stack_ptr == {(C_DATA_PTR_WIDTH){1'b1}}) && s__data_stack_valid) begin
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      $display("%12d : Data stack overflow in @CORENAME@", $time);
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      s__data_stack_error <= 1'b1;
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    end
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    if (s__N_valid && !s__T_valid) begin
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      $display("%12d : Data stack validity inversion in @CORENAME@", $time);
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      s__data_stack_error <= 1'b1;
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    end
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    if (!s__T_valid && (s_Np_stack_ptr != { {(C_DATA_PTR_WIDTH-2){1'b1}}, 2'b01 })) begin
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      $display("%12d : Malformed top-of-data-stack validity in @CORENAME@", $time);
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      s__data_stack_error <= 1'b1;
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    end
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    if (!s__N_valid && (s_Np_stack_ptr[2+:C_DATA_PTR_WIDTH-2] != {(C_DATA_PTR_WIDTH-2){1'b1}})) begin
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      $display("%12d : Malformed next-to-top-of-data-stack validity in @CORENAME@", $time);
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      s__data_stack_error <= 1'b1;
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    end
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    case (s_bus_t)
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      C_BUS_T_MATH_ROTATE:
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        if (!s__T_valid && (s_opcode[0+:3] != 3'h0)) begin
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          $display("%12d : Illegal rotate on invalid top of data stack in @CORENAME@", $time);
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          s__data_stack_error <= 1'b1;
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        end
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      C_BUS_T_ADDER:
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        if ((s_opcode[3+:4] == 4'b0011) && (!s__N_valid || !s__T_valid)) begin
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          $display("%12d : Invalid addition in @CORENAME@", $time);
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          s__data_stack_error <= 1'b1;
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        end else if (!s__T_valid) begin
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          $display("%12d : Invalid increment or decrement in @CORENAME@", $time);
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          s__data_stack_error <= 1'b1;
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        end
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      C_BUS_T_COMPARE:
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        if (!s__T_valid) begin
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          $display("%12d : Comparison on invalid top of data stack in @CORENAME@", $time);
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          s__data_stack_error <= 1'b1;
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        end
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      C_BUS_T_INPORT:
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        if (!s__T_valid) begin
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          $display("%12d : Inport using invalid top of data stack for address in @CORENAME@", $time);
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          s__data_stack_error <= 1'b1;
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        end
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      C_BUS_T_LOGIC:
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        case (s_opcode[0+:3])
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          3'b000, 3'b001, 3'b010:
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            if (!s__N_valid || !s__T_valid) begin
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              $display("%12d : Illegal logical operation in @CORENAME@", $time);
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              s__data_stack_error <= 1'b1;
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            end
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          3'b011:
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            if (!s__N_valid || !s__T_valid) begin
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              $display("%12d : Illegal nip in @CORENAME@", $time);
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              s__data_stack_error <= 1'b1;
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            end
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          3'b100, 3'b101, 3'b110, 3'b111:
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            ;
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          default:
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            ;
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        endcase
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      C_BUS_T_MEM:
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        if (!s__T_valid) begin
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          $display("%12d : Fetch using invalid top-of-data-stack in @CORENAME@", $time);
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          s__data_stack_error <= 1'b1;
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        end
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      default:
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        ;
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    endcase
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    if ((s_opcode == 9'b00_0111_000) && !s__T_valid) begin
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      $display("%12d : Outport with invalid top-of-data-stack in @CORENAME@", $time);
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      s__data_stack_error <= 1'b1;
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    end
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    if ((s_opcode == 9'b00_0111_000) && !s__N_valid && !s__outport_pure_strobe) begin
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      $display("%12d : Outport with invalid next-to-top-of-data-stack in @CORENAME@", $time);
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      s__data_stack_error <= 1'b1;
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    end
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  end
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//
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initial s__R_valid = 1'b0;
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always @ (posedge i_clk)
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  if (i_rst)
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    s__R_valid <= 1'b0;
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  else if (s_return == C_RETURN_INC)
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    s__R_valid <= 1'b1;
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  else if (s_return == C_RETURN_DEC)
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    s__R_valid <= s__return_stack_valid;
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  else
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    s__R_valid <= s__R_valid;
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//
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initial s__return_stack_valid = 1'b0;
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always @ (posedge i_clk)
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  if (i_rst)
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    s__return_stack_valid <= 1'b0;
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  else if (s_return == C_RETURN_INC)
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    s__return_stack_valid <= s__R_valid;
168 
  else if (s_return == C_RETURN_DEC)
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    if (s_R_stack_ptr == {(C_RETURN_PTR_WIDTH){1'b0}})
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      s__return_stack_valid <= 1'b0;
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    else
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      s__return_stack_valid <= s__return_stack_valid;
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  else
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    s__return_stack_valid <= s__return_stack_valid;
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//
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reg s__return_stack_error = 1'b0;
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always @ (posedge i_clk)
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  if (!s__return_stack_error) begin
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    if ((s_return == C_RETURN_DEC) && !s__R_valid) begin
180 
      $display("%12d : Return stack underflow in @CORENAME@", $time);
181 
      s__return_stack_error <= 1'b1;
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    end
183 
    if ((s_return == C_RETURN_INC) && (s_R_stack_ptr == {(C_RETURN_PTR_WIDTH){1'b1}}) && s__return_stack_valid) begin
184 
      $display("%12d : Return stack overflow in @CORENAME@", $time);
185 
      s__return_stack_error <= 1'b1;
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    end
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  end
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//
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reg s__R_is_address = 1'b0;
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reg [2**C_RETURN_PTR_WIDTH-1:0] s__return_is_address = {(2**C_RETURN_PTR_WIDTH){1'b0}};
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always @ (posedge i_clk)
192 
  if (i_rst) begin
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    s__R_is_address <= 1'b0;
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    s__return_is_address <= {(2**C_RETURN_PTR_WIDTH){1'b0}};
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  end else if (s_return == C_RETURN_INC) begin
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    s__R_is_address <= (s_bus_r == C_BUS_R_PC);
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    s__return_is_address[s_R_stack_ptr_next] <= s__R_is_address;
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  end else if (s_return == C_RETURN_DEC) begin
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    s__R_is_address <= s__return_is_address[s_R_stack_ptr];
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  end
201 
//
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reg s__R_address_error = 1'b0;
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always @ (posedge i_clk)
204 
  if (!s__R_address_error) begin
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    if ((s_bus_pc == C_BUS_PC_RETURN) && !s__R_is_address) begin
206 
      $display("%12d : Non-address by return instruction in @CORENAME@", $time);
207 
      s__R_address_error <= 1'b1;
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    end
209 
    if (((s_opcode == 9'b00_0001_001) || (s_opcode == 9'b00_1001_001)) && s__R_is_address) begin
210 
      $display("%12d : Copied address to data stack in @CORENAME@", $time);
211 
      s__R_address_error <= 1'b1;
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    end
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  end
214 
//
215 
reg s__range_error = 1'b0;
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reg [8:0] s__mem_address_limit[0:3];
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initial begin
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  s__mem_address_limit[0] = @MEM_LIMIT_0@;
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  s__mem_address_limit[1] = @MEM_LIMIT_1@;
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  s__mem_address_limit[2] = @MEM_LIMIT_2@;
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  s__mem_address_limit[3] = @MEM_LIMIT_3@;
222 
end
223 
always @ (posedge i_clk)
224 
  if ((s_opcode[3+:6] == 6'b000110) && ({ 1'b0, s_T } >= @LAST_INPORT@)) begin
225 
    $display("%12d : Range error on inport in @CORENAME@", $time);
226 
    s__range_error <= 1'b1;
227 
  end else if ((s_opcode[3+:6] == 6'b000111) && ({ 1'b0, s_T } >= @LAST_OUTPORT@)) begin
228 
    $display("%12d : Range error on outport in @CORENAME@", $time);
229 
    s__range_error <= 1'b1;
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  end else if ((s_opcode[5+:4] == 4'b0011) && ({ 1'b0, s_T } >= s__mem_address_limit[s_opcode[0+:2]])) begin
231 
    $display("%12d : Range error on memory operation in @CORENAME@", $time);
232 
    s__range_error <= 1'b1;
233 
  end
234 
//
235 
reg       [L__TRACE_SIZE-1:0] s__history[@HISTORY@-1:0];
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reg                     [8:0] s__opcode_s = 9'b0;
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reg          [C_PC_WIDTH-1:0] s__PC_s[1:0];
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integer ix__history;
239 
initial begin
240 
  for (ix__history=0; ix__history<@HISTORY@; ix__history=ix__history+1)
241 
    s__history[ix__history] = {(L__TRACE_SIZE){1'b0}};
242 
  s__PC_s[0] = {(C_PC_WIDTH){1'b0}};
243 
  s__PC_s[1] = {(C_PC_WIDTH){1'b0}};
244 
end
245 
always @ (posedge i_clk) begin
246 
  s__PC_s[1] <= s__PC_s[0];
247 
  s__PC_s[0] <= s_PC;
248 
  s__opcode_s <= s_opcode;
249 
  for (ix__history=1; ix__history<@HISTORY@; ix__history=ix__history+1)
250 
    s__history[ix__history-1] <= s__history[ix__history];
251 
  s__history[@HISTORY@-1] <= { s__PC_s[1], s__opcode_s, s_Np_stack_ptr, s__N_valid, s_N, s__T_valid, s_T, s__R_valid, s_R, s_R_stack_ptr };
252 
end
253 
wire s_terminate = s__PC_error || s__data_stack_error || s__return_stack_error || s__R_address_error || s__range_error;
254 
always @ (posedge s_terminate) begin
255 
  for (ix__history=0; ix__history<@HISTORY@; ix__history=ix__history+1)
256 
    display_trace(s__history[ix__history]);
257 
  display_trace({ s__PC_s[1], s__opcode_s, s_Np_stack_ptr, s__N_valid, s_N, s__T_valid, s_T, s__R_valid, s_R, s_R_stack_ptr });
258 
  $finish;
259 
end
260 
endgenerate

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