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sinclairrf |
################################################################################
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#
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# Copyright 2012-2013, Sinclair R.F., Inc.
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#
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################################################################################
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from ssbccPeripheral import SSBCCperipheral
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from ssbccUtil import SSBCCException;
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class open_drain(SSBCCperipheral):
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"""
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Implement an open-drain I/O suitable for direct connection to a pin. This
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can, for example, be used as an I/O port for an I2C device.\n
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Usage:
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PERIPHERAL open_drain inport=I_name \\
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outport=O_name \\
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iosignal=io_name \\
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[width=n]\n
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Where:
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inport=I_name
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is the inport symbol to read the pin
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outport=O_name
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is the outport symbol to write to the pin
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Note: A "0" value activates the open drain while a "1" value releases the
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open drain.
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iosignal=io_name
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is the tri-state pin for the open-drain I/O buffer
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Note: The initial value of the pin is "open."
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width=n
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is the optional width of the port
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Note: The default is one bit\n
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The following OUTPORTs are provided by this peripheral:
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O_name
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this is the new output for the open drain I/O\n
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The following INPORTs are provided by this peripheral:
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I_name
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this reads the current value of the open drain I/O\n
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Example: Configure two 1-bit ports implementing an I2C bus:\n
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Add the following to the architecture file:\n
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PORTCOMMENT I2C bus
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PERIPHERAL open_drain inport=I_SCL outport=O_SCL iosignal=io_scl
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PERIPHERAL open_drain inport=I_SDA outport=O_SDA iosignal=io_sda\n
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The following assembly will transmit the start condition for an I2C bus by
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pulling SDA low and then pulling SCL low.\n
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; Set SDA low
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; delay one fourth of a 400 kHz cycle (based on a 100 MHz clock)
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${int(100.e6/400.e3/3)-1} :delay .jumpc(delay,1-) drop
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; Set SCL low
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See the I2C examples for a complete demonstration of using the open_drain
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peripheral.
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"""
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def __init__(self,peripheralFile,config,param_list,loc):
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# Use the externally provided file name for the peripheral
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self.peripheralFile = peripheralFile;
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# Parse the parameters.
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for param_tuple in param_list:
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param = param_tuple[0];
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param_arg = param_tuple[1];
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if param == 'inport':
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self.AddAttr(config,param,param_arg,r'I_\w+$',loc);
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elif param == 'iosignal':
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self.AddAttr(config,param,param_arg,r'io_\w+$',loc);
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elif param == 'outport':
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self.AddAttr(config,param,param_arg,r'O_\w+$',loc);
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elif param == 'width':
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self.AddAttr(config,param,param_arg,r'[1-9]\d*$',loc,int);
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else:
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raise SSBCCException('Unrecognized parameter at %s: "%s"' % (loc,param,));
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# Ensure the required parameters are set.
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if not hasattr(self,'inport'):
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raise SSBCCException('Missing "inport=I_name" at %s' % loc);
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if not hasattr(self,'iosignal'):
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raise SSBCCException('Missing "iosignal=io_name" at %s' % loc);
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if not hasattr(self,'outport'):
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raise SSBCCException('Missing "outport=O_name" at %s' % loc);
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# Set defaults for non-specified values.
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if not hasattr(self,'width'):
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self.width = 1;
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# Ensure the specified values are reasonable.
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maxWidth = config.Get('data_width');
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if (self.width < 1) or (maxWidth < self.width):
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raise SSBCCException('width must be between 1 and %d inclusive at %s' % (maxWidth,loc,));
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# Create the internal signal name and initialization.
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self.sname = 's__%s' % self.iosignal;
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sname_init = '%d\'b%s' % (self.width, '1'*self.width, );
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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config.AddIO(self.iosignal,self.width,'inout',loc);
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config.AddSignalWithInit(self.sname,self.width,None,loc);
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config.AddInport((self.inport,
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(self.iosignal,self.width,'data',),
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),
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loc);
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config.AddOutport((self.outport,False,
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(self.sname,self.width,'data',sname_init,),
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),
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loc);
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def GenVerilog(self,fp,config):
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body_1 = """//
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// PERIPHERAL open_drain: @NAME@
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//
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assign @IO_NAME@ = (@S_NAME@ == 1'b0) ? 1'b0 : 1'bz;
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"""
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body_big = """//
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// PERIPHERAL open_drain: @NAME@
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//
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generate
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genvar ix;
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for (ix=0; ix<@WIDTH@; ix = ix+1) begin : gen_@NAME@
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assign @IO_NAME@[ix] = (@S_NAME@[ix] == 1'b0) ? 1'b0 : 1'bz;
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end
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endgenerate
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"""
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if self.width == 1:
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body = body_1;
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else:
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body = body_big;
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for subs in (
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(r'\bix\b', 'ix__@NAME@',),
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(r'@IO_NAME@', self.iosignal,),
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(r'@NAME@', self.iosignal,),
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(r'@S_NAME@', self.sname,),
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(r'@WIDTH@', str(self.width),),
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):
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body = re.sub(subs[0],subs[1],body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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