1 |
2 |
sinclairrf |
################################################################################
|
2 |
|
|
#
|
3 |
6 |
sinclairrf |
# Copyright 2013-2014, Sinclair R.F., Inc.
|
4 |
2 |
sinclairrf |
#
|
5 |
|
|
################################################################################
|
6 |
|
|
|
7 |
|
|
import math;
|
8 |
|
|
import re;
|
9 |
|
|
|
10 |
|
|
from ssbccPeripheral import SSBCCperipheral
|
11 |
|
|
from ssbccUtil import CeilLog2;
|
12 |
|
|
from ssbccUtil import IsPowerOf2;
|
13 |
|
|
from ssbccUtil import SSBCCException;
|
14 |
|
|
|
15 |
|
|
class outFIFO_async(SSBCCperipheral):
|
16 |
|
|
"""
|
17 |
|
|
Output FIFO with an asynchronous clock.\n
|
18 |
|
|
Usage:
|
19 |
|
|
PERIPHERAL outFIFO_async outclk=<i_clock> \\
|
20 |
|
|
data=<o_data> \\
|
21 |
|
|
data_rd=<i_data_rd> \\
|
22 |
|
|
data_empty=<o_data_empty> \\
|
23 |
|
|
outport=<O_data> \\
|
24 |
|
|
infull=<I_full> \\
|
25 |
12 |
sinclairrf |
depth=<N> \\
|
26 |
|
|
[outempty=I_empty] \n
|
27 |
2 |
sinclairrf |
Where:
|
28 |
|
|
outclk=<i_clock>
|
29 |
|
|
specifies the name of the asynchronous read clock
|
30 |
|
|
data=<o_data>
|
31 |
|
|
specifies the name of the 8-bit outgoing data
|
32 |
|
|
data_rd=<i_data_rd>
|
33 |
|
|
specifies the name if the read strobe
|
34 |
|
|
data_empty=<o_data_empty>
|
35 |
|
|
specifies the name of the output "empty" status of the FIFO
|
36 |
|
|
outport=<O_data>
|
37 |
|
|
specifies the name of the port to write to the FIFO
|
38 |
|
|
infull=<I_full>
|
39 |
|
|
specifies the symbol used by the inport instruction to read the "full"
|
40 |
|
|
status of the FIFO
|
41 |
|
|
depth=<N>
|
42 |
|
|
specifies the depth of the FIFO
|
43 |
12 |
sinclairrf |
Note: N must be a power of 2 and must be at least 16.
|
44 |
|
|
outempty=O_empty
|
45 |
|
|
optionally specifies the name of an input port for the processor to access
|
46 |
|
|
the "empty" status of the FIFO\n
|
47 |
2 |
sinclairrf |
Example: Provide a FIFO to an external device or IP.\n
|
48 |
|
|
The PERIPHERAL statement would be:\n
|
49 |
|
|
PERIPHERAL outFIFO_async outclk=i_dev_clk \\
|
50 |
|
|
data=o_dev_data \\
|
51 |
|
|
data_rd=i_dev_data_rd \\
|
52 |
|
|
data_empty=o_dev_empty \\
|
53 |
|
|
outport=O_DATA_FIFO \\
|
54 |
|
|
infull=I_DATA_FIFO_FULL \\
|
55 |
|
|
depth=32\n
|
56 |
|
|
To put a text message in the FIFO, similarly to a UART, do the following:\n
|
57 |
|
|
N"message"
|
58 |
|
|
:loop
|
59 |
|
|
.inport(I_DATA_FIFO_FULL) .jumpc(loop)
|
60 |
|
|
.outport(O_DATA_FIFO)
|
61 |
12 |
sinclairrf |
.jumpc(loop,nop)\n
|
62 |
|
|
Interrupt handler: "!s__<data>__outempty_in" is is suitable input to an
|
63 |
|
|
interrupt handler where "<data>" is the name assigned to "data". This signal
|
64 |
|
|
is high when the FIFO is empty, so a falling edge (the leading "!") is a
|
65 |
|
|
suitable condition for the interrupt to occur.
|
66 |
2 |
sinclairrf |
"""
|
67 |
|
|
|
68 |
|
|
def __init__(self,peripheralFile,config,param_list,loc):
|
69 |
|
|
# Use the externally provided file name for the peripheral
|
70 |
|
|
self.peripheralFile = peripheralFile;
|
71 |
|
|
# Get the parameters.
|
72 |
|
|
allowables = (
|
73 |
|
|
('outclk', r'i_\w+$', None, ),
|
74 |
|
|
('data', r'o_\w+$', None, ),
|
75 |
|
|
('data_rd', r'i_\w+$', None, ),
|
76 |
|
|
('data_empty', r'o_\w+$', None, ),
|
77 |
|
|
('outport', r'O_\w+$', None, ),
|
78 |
|
|
('infull', r'I_\w+$', None, ),
|
79 |
9 |
sinclairrf |
('depth', r'[1-9]\d*$', lambda v : self.IntPow2Method(config,v,lowLimit=16), ),
|
80 |
12 |
sinclairrf |
('outempty', r'I_\w+$', None, ),
|
81 |
2 |
sinclairrf |
);
|
82 |
|
|
names = [a[0] for a in allowables];
|
83 |
|
|
for param_tuple in param_list:
|
84 |
|
|
param = param_tuple[0];
|
85 |
|
|
if param not in names:
|
86 |
|
|
raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
|
87 |
|
|
param_test = allowables[names.index(param)];
|
88 |
|
|
self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
|
89 |
|
|
# Ensure the required parameters are provided.
|
90 |
|
|
for paramname in names:
|
91 |
12 |
sinclairrf |
if paramname in ('outempty',):
|
92 |
|
|
continue;
|
93 |
2 |
sinclairrf |
if not hasattr(self,paramname):
|
94 |
|
|
raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
|
95 |
|
|
# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
|
96 |
|
|
config.AddIO(self.outclk,1,'input',loc);
|
97 |
|
|
config.AddIO(self.data,8,'output',loc);
|
98 |
|
|
config.AddIO(self.data_rd,1,'input',loc);
|
99 |
|
|
config.AddIO(self.data_empty,1,'output',loc);
|
100 |
|
|
config.AddSignal('s__%s__full' % self.data,1,loc);
|
101 |
|
|
self.ix_outport = config.NOutports();
|
102 |
|
|
config.AddOutport((self.outport,False,
|
103 |
|
|
# empty list
|
104 |
|
|
),loc);
|
105 |
|
|
config.AddInport((self.infull,
|
106 |
|
|
('s__%s__full' % self.data,1,'data',),
|
107 |
|
|
),loc);
|
108 |
|
|
|
109 |
12 |
sinclairrf |
if hasattr(self,'outempty'):
|
110 |
|
|
self.outempty_name = 's__%s__outempty_in' % self.data;
|
111 |
|
|
config.AddSignalWithInit(self.outempty_name,1,'1\'b1',loc);
|
112 |
|
|
self.ix_outempty = config.NInports();
|
113 |
|
|
config.AddInport((self.outempty,
|
114 |
|
|
(self.outempty_name,1,'data',),
|
115 |
|
|
),loc);
|
116 |
|
|
|
117 |
2 |
sinclairrf |
def GenVerilog(self,fp,config):
|
118 |
|
|
body = self.LoadCore(self.peripheralFile,'.v');
|
119 |
12 |
sinclairrf |
if hasattr(self,'outempty'):
|
120 |
|
|
body_outempty = """\
|
121 |
|
|
always @ (posedge i_clk)
|
122 |
|
|
s__outempty_in <= (s__delta_clk == @DEPTH_NBITS@'d0);
|
123 |
|
|
"""
|
124 |
|
|
else:
|
125 |
|
|
body_outempty = '';
|
126 |
2 |
sinclairrf |
for subpair in (
|
127 |
12 |
sinclairrf |
( r'@OUTEMPTY@\n', body_outempty, ),
|
128 |
6 |
sinclairrf |
( r'@DATA@', self.data, ),
|
129 |
|
|
( r'@DATA_EMPTY@', self.data_empty, ),
|
130 |
|
|
( r'@DATA_RD@', self.data_rd, ),
|
131 |
|
|
( r'@DEPTH@', str(self.depth), ),
|
132 |
|
|
( r'@DEPTH-1@', str(self.depth-1), ),
|
133 |
|
|
( r'@DEPTH_NBITS@', str(CeilLog2(self.depth)), ),
|
134 |
|
|
( r'@DEPTH_NBITS-1@', str(CeilLog2(self.depth)-1), ),
|
135 |
|
|
( r'@OUTCLK@', self.outclk, ),
|
136 |
|
|
( r'@IX_OUTPORT@', str(self.ix_outport), ),
|
137 |
|
|
( r'@NAME@', self.data, ),
|
138 |
|
|
( r'\bgen__', 'gen__%s__' % self.data, ),
|
139 |
|
|
( r'\bix__', 'ix__%s__' % self.data, ),
|
140 |
|
|
( r'\bs__', 's__%s__' % self.data, ),
|
141 |
|
|
):
|
142 |
2 |
sinclairrf |
body = re.sub(subpair[0],subpair[1],body);
|
143 |
|
|
body = self.GenVerilogFinal(config,body);
|
144 |
|
|
fp.write(body);
|