Subversion Repositories ssbcc

# Copyright 2013, Sinclair R.F., Inc.

# Test bench for AXI4-Lite master peripheral.

ARCHITECTURE core/9x8 Verilog

INSTRUCTION     128

DATA_STACK      16

RETURN_STACK    2

PORTCOMMENT AXI4-Lite Master

LOCALPARAM L_DP_SIZE 128

PERIPHERAL AXI4_Lite_Master                             \

                        basePortName=alm                \

                        address=O_ALM_ADDRESS           \

                        data=O_ALM_DATA                 \

                        write_enable=O_ALM_WE           \

                        command_read=O_ALM_CMD_READ     \

                        command_write=O_ALM_CMD_WRITE   \

                        busy=I_ALM_BUSY                 \

                        error=I_ALM_ERROR               \

                        read=I_ALM_READ_BYTE            \

                        address_width=7                 \

                        synchronous=True

PORTCOMMENT diagnostic output

OUTPORT 8-bit,strobe    o_diag_data,o_diag_wr   O_DIAG_DATA

PORTCOMMENT program termination

OUTPORT strobe o_done O_DONE

ASSEMBLY tb_AXI4_Lite_Master.s