OpenCores
URL https://opencores.org/ocsvn/ssbcc/ssbcc/trunk

Subversion Repositories ssbcc

[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [AXI4_Lite_Slave_DualPortRAM/] [master.gtkw] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 sinclairrf
[*]
2
[*] GTKWave Analyzer v3.3.42 (w)1999-2012 BSI
3
[*] Sun Mar 23 13:48:13 2014
4
[*]
5
[dumpfile] "/home/rsinclair/Projects/SSBCC/core/9x8/peripherals/tb/AXI4_Lite_Slave_DualPortRAM/tb.vcd"
6
[dumpfile_mtime] "Sun Mar 23 12:59:00 2014"
7
[dumpfile_size] 869113
8
[savefile] "/home/rsinclair/Projects/SSBCC/core/9x8/peripherals/tb/AXI4_Lite_Slave_DualPortRAM/master.gtkw"
9
[timestart] 20022900
10
[size] 1920 1171
11
[pos] -1 -1
12
*-16.801830 20420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
13
[treeopen] tb.
14
[treeopen] tb.uut.
15
[sst_width] 205
16
[signals_width] 276
17
[sst_expanded] 1
18
[sst_vpaned_height] 353
19
@28
20
tb.uut.i_axi_lite_aclk
21
tb.uut.i_axi_lite_aresetn
22
@200
23
-write side
24
@22
25
tb.uut.i_axi_lite_awaddr[6:0]
26
tb.uut.i_axi_lite_wdata[31:0]
27
tb.uut.i_axi_lite_wstrb[3:0]
28
@28
29
tb.uut.o_axi_lite_awready
30
tb.uut.i_axi_lite_awvalid
31
tb.uut.o_axi_lite_wready
32
tb.uut.i_axi_lite_wvalid
33
tb.uut.i_axi_lite_bready
34
tb.uut.o_axi_lite_bvalid
35
tb.uut.o_axi_lite_bresp[1:0]
36
@200
37
-read side
38
@22
39
tb.uut.i_axi_lite_araddr[6:0]
40
@29
41
tb.uut.o_axi_lite_arready
42
@28
43
tb.uut.i_axi_lite_arvalid
44
tb.uut.i_axi_lite_rready
45
tb.uut.o_axi_lite_rvalid
46
tb.uut.o_axi_lite_rresp[1:0]
47
@22
48
tb.uut.o_axi_lite_rdata[31:0]
49
[pattern_trace] 1
50
[pattern_trace] 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.