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#

# Copyright 2012, Sinclair R.F., Inc.

#

# Test bench for PWM_8bit peripheral.

#

ARCHITECTURE    core/9x8 Verilog

INSTRUCTION     128

DATA_STACK      32

RETURN_STACK    16

PARAMETER       G_CLK_FREQ_HZ   100_000_000

PORTCOMMENT allow runts

PERIPHERAL      PWM_8bit        outport=O_PWM_SR \

                                outsignal=o_pwm_sr \

                                ratemethod=G_CLK_FREQ_HZ/(6000*255)

PORTCOMMENT no-runt PWM

PERIPHERAL      PWM_8bit        outport=O_PWM_SN \

                                outsignal=o_pwm_sn \

                                ratemethod=G_CLK_FREQ_HZ/(6000*255) \

                                norunt

PORTCOMMENT inverted output PWM

PERIPHERAL      PWM_8bit        outport=O_PWM_SI \

                                outsignal=o_pwm_si \

                                ratemethod=G_CLK_FREQ_HZ/(6000*255) \

                                invert

PORTCOMMENT 3-channel PWM

PERIPHERAL      PWM_8bit        outport=O_PWM_MULTI \

                                outsignal=o_pwm_multi \

                                ratemethod=100_000_000/(6000*255) \

                                instances=3

PORTCOMMENT termination signal

OUTPORT 1-bit o_done O_DONE

ASSEMBLY tb_PWM_8bit.s