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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [PWM_8bit/] [tb_PWM_8bit.9x8] - Blame information for rev 13

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Line No. Rev Author Line
1 2 sinclairrf 
#
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# Copyright 2012, Sinclair R.F., Inc.
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#
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# Test bench for PWM_8bit peripheral.
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#
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ARCHITECTURE    core/9x8 Verilog
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INSTRUCTION     128
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DATA_STACK      32
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RETURN_STACK    16
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PARAMETER       G_CLK_FREQ_HZ   100_000_000
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CONSTANT        C_PWM_CLK_HZ    6000*255
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PORTCOMMENT allow runts
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PERIPHERAL      PWM_8bit        outport=O_PWM_SR \
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                                outsignal=o_pwm_sr \
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                                ratemethod=G_CLK_FREQ_HZ/C_PWM_CLK_HZ
19 2 sinclairrf 
 
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PORTCOMMENT no-runt PWM
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PERIPHERAL      PWM_8bit        outport=O_PWM_SN \
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                                outsignal=o_pwm_sn \
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                                ratemethod=G_CLK_FREQ_HZ/C_PWM_CLK_HZ \
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                                norunt
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PORTCOMMENT inverted output PWM
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PERIPHERAL      PWM_8bit        outport=O_PWM_SI \
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                                outsignal=o_pwm_si \
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                                ratemethod=G_CLK_FREQ_HZ/C_PWM_CLK_HZ \
30 2 sinclairrf 
                                invert
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PORTCOMMENT 3-channel PWM
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PERIPHERAL      PWM_8bit        outport=O_PWM_MULTI \
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                                outsignal=o_pwm_multi \
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                                ratemethod=100_000_000/C_PWM_CLK_HZ \
36 2 sinclairrf 
                                instances=3
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PORTCOMMENT termination signal
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OUTPORT 1-bit o_done O_DONE
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ASSEMBLY tb_PWM_8bit.s

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