Subversion Repositories ssbcc

# Copyright 2013, Sinclair R.F., Inc.

# Test bench for UART peripheral.

ARCHITECTURE    core/9x8 Verilog

INSTRUCTION     64

DATA_STACK      16

RETURN_STACK    2

PARAMETER       G_CLK_FREQ_HZ   10_000_000

PARAMETER       G_BAUD          115200

PORTCOMMENT UART1

PERIPHERAL      UART    inport=I_UART1_Rx \

                        outport=O_UART1_Tx \

                        inempty=I_UART1_RX_EMPTY \

                        outstatus=I_UART1_TX_BUSY \

                        baudmethod=G_CLK_FREQ_HZ/G_BAUD \

                        insignal=i_uart1_rx \

                        outsignal=o_uart1_tx \

                        outFIFO=16 \

                        nStop=2

PORTCOMMENT UART2

PERIPHERAL      UART    inport=I_UART2_Rx \

                        outport=O_UART2_Tx \

                        inempty=I_UART2_RX_EMPTY \

                        outstatus=I_UART2_TX_BUSY \

                        baudmethod=G_CLK_FREQ_HZ/230400 \

                        insignal=i_uart2_rx \

                        outsignal=o_uart2_tx \

                        inFIFO=16

PORTCOMMENT output data

OUTPORT 8-bit,strobe o_data,o_data_wr O_DATA

PORTCOMMENT program termination

OUTPORT 1-bit o_done O_DONE

ASSEMBLY tb_UART.s