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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [UART_Rx/] [tb_UART_Rx.9x8-good] - Blame information for rev 2

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# Copyright 2013, Sinclair R.F., Inc.
# Test bench for UART_Rx peripheral.
 
ARCHITECTURE    core/9x8 Verilog
INSTRUCTION     64
DATA_STACK      8
RETURN_STACK    2
 
PARAMETER       G_CLK_FREQ_HZ   100_000_000
PARAMETER       G_BAUD          115200
 
PERIPHERAL      UART_Rx         inport=I_UART_RX \
                                inempty=I_UART_RX_EMPTY \
                                insignal=i_uart \
                                baudmethod=G_CLK_FREQ_HZ/G_BAUD
 
OUTPORT 8-bit,strobe o_data,o_data_wr O_DATA
 
OUTPORT 1-bit o_done O_DONE
 
ASSEMBLY tb_UART_Rx.s

Line No.	Rev	Author	Line
1	2	sinclairrf	`# Copyright 2013, Sinclair R.F., Inc.`
2			`# Test bench for UART_Rx peripheral.`
3
4			`ARCHITECTURE core/9x8 Verilog`
5			`INSTRUCTION 64`
6			`DATA_STACK 8`
7			`RETURN_STACK 2`
8
9			`PARAMETER G_CLK_FREQ_HZ 100_000_000`
10			`PARAMETER G_BAUD 115200`
11
12			`PERIPHERAL UART_Rx inport=I_UART_RX \`
13			`inempty=I_UART_RX_EMPTY \`
14			`insignal=i_uart \`
15			`baudmethod=G_CLK_FREQ_HZ/G_BAUD`
16
17			`OUTPORT 8-bit,strobe o_data,o_data_wr O_DATA`
18
19			`OUTPORT 1-bit o_done O_DONE`
20
21			`ASSEMBLY tb_UART_Rx.s`

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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [UART_Rx/] [tb_UART_Rx.9x8-good] - Blame information for rev 2