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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [UART_Tx/] [tb.awk] - Blame information for rev 2

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Line No. Rev Author Line
1 2 sinclairrf
#!/usr/bin/gawk
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# Copyright 2012, Sinclair R.F., Inc.
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#
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# Parse the output of the Verilog test bench to ensure the signals transmit
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# "Hello World!" and the proper baud and number of stop bits.
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function abs(a) {
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  return (a>=0) ? a : -a;
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}
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function append_state() {
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  dt = t_cur-state[ix,"t_last"];
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  nbits = int(dt/dtBaud);
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  if (dt-nbits*dtBaud > 0.5*dtBaud) ++nbits;
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  dt -= nbits*dtBaud;
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  for (jx=0; jx<nbits; ++jx)
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    state[ix,"cur"] = state[ix,"cur"] state[ix,"last"];
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}
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function convert_state(_v) {
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  _v = 0;
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  for (jx=0; jx<8; ++jx) {
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    _v /= 2;
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    _v += strtonum(substr(state[ix,"cur"],2+jx,1))*0x80;
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  }
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  state[ix,"cur"] = "";
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  return sprintf("%c",_v);
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}
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BEGIN {
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  first = 1;
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  for (ix=1; ix<=3; ++ix) {
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    state[ix,"mode"] = -1;
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    state[ix,"msg"] = "";
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    state[ix,"nStop"] = 1;
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    state[ix,"last"] = 1;
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  }
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  state[3,"nStop"] = 2;
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  dtBaud = 1./115200;
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  dtTol = 1./100e6/2;
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}
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{
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  t_cur = $1/1.e9;
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  if (first > 0) {
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    --first;
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    for (ix=1; ix<=3; ++ix)
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      state[ix,"t_last"] = t_cur;
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    next;
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  }
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  for (ix=1; ix<=3; ++ix) {
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    this = $(ix+2);
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    if (this == state[ix,"last"])
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      continue;
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    if (state[ix,"mode"] == -1) {
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      if (this != "0") {
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        print "Missing start bit at line",FNR > "/dev/stderr";
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        exit(1);
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      } else {
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        state[ix,"t_last"] = t_cur;
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        state[ix,"mode"] = 0;
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        state[ix,"last"] = "0";
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        state[ix,"cur"] = "";
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      }
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    } else {
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      append_state();
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      if (length(state[ix,"cur"]) < 9+state[ix,"nStop"]) {
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        if (abs(dt)>dtTol*nbits) {
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          print "Baud rate out of tolerance at line",FNR > "/dev/stderr";
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          exit(1);
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        }
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      } else if (length(state[ix,"cur"]) == 9+state[ix,"nStop"]) {
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        if (dt < -dtTol*nbits) {
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          print "Baud rate out of tolerance at line",FNR > "/dev/stderr";
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          exit(1);
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        }
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        state[ix,"msg"] = state[ix,"msg"] convert_state();
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      } else {
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      }
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    }
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    state[ix,"t_last"] = t_cur;
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    state[ix,"last"] = this;
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  }
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}
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END {
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  t_cur = $1/1.e9;
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  for (ix=1; ix<=3; ++ix) {
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    append_state();
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    state[ix,"msg"] = state[ix,"msg"] convert_state();
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  }
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  for (ix=1; ix<=3; ++ix)
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    print ix, state[ix,"msg"];
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}

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