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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [UART_Tx/] [tb_UART_Tx.s] - Blame information for rev 2

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Line No. Rev Author Line
1 2 sinclairrf
; Copyright 2012, Sinclair R.F., Inc.
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;
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; Test bench for UART_Tx peripheral.
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.main
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  .call(load_message) :loop1 .outport(O_UART1_TX) .jumpc(loop1,nop) drop
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  .call(load_message) :loop2 .outport(O_UART2_TX) .jumpc(loop2,nop) drop
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  .call(load_message) :loop3 .outport(O_UART3_TX) :wait3 .inport(I_UART3_TX) .jumpc(wait3) .jumpc(loop3,nop) drop
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  :wait .inport(I_UART3_TX) .jumpc(wait)
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  1 .outport(O_DONE)
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  :infinite .jump(infinite)
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.function load_message
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  N"ello World!"
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.return('H')

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