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#

# Copyright 2013-2014, Sinclair R.F., Inc.

#

# Test bench for big_inport peripheral.

#

ARCHITECTURE    core/9x8 Verilog

INSTRUCTION     128

DATA_STACK      32

RETURN_STACK    16

PORTCOMMENT     very big inport signal

PERIPHERAL      big_inport      outlatch=O_VB_LATCH     \

                                inport=I_VB             \

                                insignal=i_vb           \

                                width=26

PORTCOMMENT     minimal big inport signal

PERIPHERAL      big_inport      outlatch=O_MIN_LATCH    \

                                inport=I_MIN            \

                                insignal=i_min          \

                                width=9

PORTCOMMENT     diagnostic echo of received value

OUTPORT         8-bit,strobe    o_diag,o_diag_wr        O_DIAG

PORTCOMMENT     termination signal

OUTPORT         1-bit           o_done                  O_DONE

ASSEMBLY tb_big_inport.s