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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [big_inport/] [tb_big_inport.s] - Blame information for rev 12

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; Copyright 2013, Sinclair R.F., Inc.
;
; Test bench for big_output peripheral.
 
.main
 
  ; Read a 26-bit value
  .outstrobe(O_VB_LATCH)
  .inport(I_VB)
  .inport(I_VB)
  .inport(I_VB)
  .inport(I_VB)
 
  ; Read a 9-bit value
  .outstrobe(O_MIN_LATCH)
  .inport(I_MIN)
  .inport(I_MIN)
 
  ; Dump all 6 bytes to the test bench
  ${6-1} :loop swap .outport(O_DIAG) .jumpc(loop,1-) drop
 
  ; Wait a few clock cycles.
  ${3-1} :wait .jumpc(wait,1-) drop
 
  ; Send the termination signal and then enter an infinite loop.
  1 .outport(O_DONE)
  :infinite .jump(infinite)

Line No.	Rev	Author	Line
1	2	sinclairrf	`; Copyright 2013, Sinclair R.F., Inc.`
2			`;`
3			`; Test bench for big_output peripheral.`
4
5			`.main`
6
7			`; Read a 26-bit value`
8			`.outstrobe(O_VB_LATCH)`
9			`.inport(I_VB)`
10			`.inport(I_VB)`
11			`.inport(I_VB)`
12			`.inport(I_VB)`
13
14			`; Read a 9-bit value`
15			`.outstrobe(O_MIN_LATCH)`
16			`.inport(I_MIN)`
17			`.inport(I_MIN)`
18
19			`; Dump all 6 bytes to the test bench`
20			`${6-1} :loop swap .outport(O_DIAG) .jumpc(loop,1-) drop`
21
22			`; Wait a few clock cycles.`
23			`${3-1} :wait .jumpc(wait,1-) drop`
24
25			`; Send the termination signal and then enter an infinite loop.`
26			`1 .outport(O_DONE)`
27			`:infinite .jump(infinite)`

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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [big_inport/] [tb_big_inport.s] - Blame information for rev 12