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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [big_outport/] [tb_big_outport.9x8] - Blame information for rev 3

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#
# Copyright 2013-2014, Sinclair R.F., Inc.
#
# Test bench for big_outport peripheral.
#
 
ARCHITECTURE    core/9x8 Verilog
INSTRUCTION     128
DATA_STACK      32
RETURN_STACK    16
 
PORTCOMMENT     very big outport signal
PERIPHERAL      big_outport     outport=O_VB    \
                                outsignal=o_vb  \
                                width=26
OUTPORT         strobe  o_wr_26bit      O_WR_26BIT
OUTPORT         strobe  o_wr_18bit      O_WR_18BIT
 
PORTCOMMENT     minimal composite signal
PERIPHERAL      big_outport     outport=O_MIN   \
                                outsignal=o_min \
                                width=9
OUTPORT         strobe  o_wr_9bit       O_WR_9BIT
 
PORTCOMMENT termination signal
OUTPORT 1-bit o_done O_DONE
 
ASSEMBLY tb_big_outport.s

Line No.	Rev	Author	Line
1	2	sinclairrf	`#`
2	3	sinclairrf	`# Copyright 2013-2014, Sinclair R.F., Inc.`
3	2	sinclairrf	`#`
4	3	sinclairrf	`# Test bench for big_outport peripheral.`
5	2	sinclairrf	`#`
6
7			`ARCHITECTURE core/9x8 Verilog`
8			`INSTRUCTION 128`
9			`DATA_STACK 32`
10			`RETURN_STACK 16`
11
12			`PORTCOMMENT very big outport signal`
13			`PERIPHERAL big_outport outport=O_VB \`
14			`outsignal=o_vb \`
15			`width=26`
16			`OUTPORT strobe o_wr_26bit O_WR_26BIT`
17			`OUTPORT strobe o_wr_18bit O_WR_18BIT`
18
19			`PORTCOMMENT minimal composite signal`
20			`PERIPHERAL big_outport outport=O_MIN \`
21			`outsignal=o_min \`
22			`width=9`
23			`OUTPORT strobe o_wr_9bit O_WR_9BIT`
24
25			`PORTCOMMENT termination signal`
26			`OUTPORT 1-bit o_done O_DONE`
27
28			`ASSEMBLY tb_big_outport.s`

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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [big_outport/] [tb_big_outport.9x8] - Blame information for rev 3