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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [inFIFO_async/] [tb_inFIFO_async.9x8] - Blame information for rev 2

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1 2 sinclairrf
#
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# Copyright 2013, Sinclair R.F., Inc.
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#
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# Test bench for PWM_8bit peripheral.
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#
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ARCHITECTURE    core/9x8 Verilog
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INSTRUCTION     256
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DATA_STACK      64
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RETURN_STACK    64
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PORTCOMMENT     asynchronous input FIFO
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PERIPHERAL      inFIFO_async    inclk=i_aclk            \
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                                data=i_data             \
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                                data_wr=i_data_wr       \
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                                data_full=o_data_full   \
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                                inport=I_DATA           \
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                                inempty=I_EMPTY         \
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                                depth=32
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PORTCOMMENT     diagnostic echo of received value
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OUTPORT         8-bit,strobe    o_diag,o_diag_wr        O_DIAG
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PORTCOMMENT     termination signal
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OUTPORT         1-bit           o_done                  O_DONE
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ASSEMBLY tb_inFIFO_async.s

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