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#

# Copyright 2013, Sinclair R.F., Inc.

#

# Test bench for PWM_8bit peripheral.

#

ARCHITECTURE    core/9x8 Verilog

INSTRUCTION     256

DATA_STACK      64

RETURN_STACK    64

PORTCOMMENT     asynchronous input FIFO

PERIPHERAL      inFIFO_async    inclk=i_aclk            \

                                data=i_data             \

                                data_wr=i_data_wr       \

                                data_full=o_data_full   \

                                inport=I_DATA           \

                                inempty=I_EMPTY         \

                                depth=32

PORTCOMMENT     diagnostic echo of received value

OUTPORT         8-bit,strobe    o_diag,o_diag_wr        O_DIAG

PORTCOMMENT     termination signal

OUTPORT         1-bit           o_done                  O_DONE

ASSEMBLY tb_inFIFO_async.s