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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [inFIFO_async/] [tb_inFIFO_async.s] - Blame information for rev 2

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1 2 sinclairrf
; Copyright 2013, Sinclair R.F., Inc.
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;
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; Test bench for big_output peripheral.
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.main
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  ; Wait a few clock cycles.
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  ${3-1} :wait0 .jumpc(wait0,1-) drop
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  ; Read and output 10 values from the FIFO.
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  ${10-1} :loop10
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    .inport(I_EMPTY) .jumpc(loop10)
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    .inport(I_DATA) .outport(O_DIAG)
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  .jumpc(loop10,1-) drop
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  ; Wait long enough for the FIFO to get full.
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  ${15-1} :wait1 .jumpc(wait1,1-) drop
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  ; Read a burst of 40 data values from the FIFO as fast as possible.
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  .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA)
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  .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA)
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  .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA)
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  .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA)
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  .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA)
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  .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA)
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  .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA)
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  .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA) .inport(I_DATA)
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  ; Move these 40 values to the return stack.
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  ${40-1} :move40 swap >r .jumpc(move40,1-) drop
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  ; Write the 40 values to the output port in the order they were received.
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  ${40-1} :loop40 r> .outport(O_DIAG) .jumpc(loop40,1-) drop
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  ; Wait a few clock cycles.
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  ${3-1} :wait2 .jumpc(wait2,1-) drop
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  ; Send the termination signal and then enter an infinite loop.
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  1 .outport(O_DONE)
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  :infinite .jump(infinite)

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