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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [interrupt/] [tb_interrupt.9x8] - Blame information for rev 12

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# Copyright 2015, Sinclair R.F., Inc.
# Test bench for interrupt peripheral.
 
ARCHITECTURE    core/9x8 Verilog
ASSEMBLY        tb_interrupt.s
 
INSTRUCTION     256
DATA_STACK      16
RETURN_STACK    16
 
PERIPHERAL trace
 
PORTCOMMENT     external interrupt
PERIPHERAL      interrupt       insignal0=i_interrupt

Line No.	Rev	Author	Line
1	12	sinclairrf	`# Copyright 2015, Sinclair R.F., Inc.`
2			`# Test bench for interrupt peripheral.`
3
4			`ARCHITECTURE core/9x8 Verilog`
5			`ASSEMBLY tb_interrupt.s`
6
7			`INSTRUCTION 256`
8			`DATA_STACK 16`
9			`RETURN_STACK 16`
10
11			`PERIPHERAL trace`
12
13			`PORTCOMMENT external interrupt`
14			`PERIPHERAL interrupt insignal0=i_interrupt`

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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [interrupt/] [tb_interrupt.9x8] - Blame information for rev 12