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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [latch/] [tb_latch.9x8] - Blame information for rev 2

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#
# Copyright 2012, Sinclair R.F., Inc.
#
# Test bench for latch peripheral.
#
 
ARCHITECTURE    core/9x8 Verilog
INSTRUCTION     64
DATA_STACK      32
RETURN_STACK    16
 
PERIPHERAL      latch           outport_latch=O_9LATCH \
                                outport_addr=O_9ADDR \
                                inport=I_9READ \
                                insignal=i_9value \
                                width=9
 
PERIPHERAL      latch           outport_latch=O_24LATCH \
                                outport_addr=O_24ADDR \
                                inport=I_24READ \
                                insignal=i_24value \
                                width=24
 
OUTPORT 8-bit,strobe o_test,o_test_wr O_TEST
 
OUTPORT 1-bit o_done O_DONE
 
ASSEMBLY tb_latch.s

Line No.	Rev	Author	Line
1	2	sinclairrf	`#`
2			`# Copyright 2012, Sinclair R.F., Inc.`
3			`#`
4			`# Test bench for latch peripheral.`
5			`#`
6
7			`ARCHITECTURE core/9x8 Verilog`
8			`INSTRUCTION 64`
9			`DATA_STACK 32`
10			`RETURN_STACK 16`
11
12			`PERIPHERAL latch outport_latch=O_9LATCH \`
13			`outport_addr=O_9ADDR \`
14			`inport=I_9READ \`
15			`insignal=i_9value \`
16			`width=9`
17
18			`PERIPHERAL latch outport_latch=O_24LATCH \`
19			`outport_addr=O_24ADDR \`
20			`inport=I_24READ \`
21			`insignal=i_24value \`
22			`width=24`
23
24			`OUTPORT 8-bit,strobe o_test,o_test_wr O_TEST`
25
26			`OUTPORT 1-bit o_done O_DONE`
27
28			`ASSEMBLY tb_latch.s`

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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [latch/] [tb_latch.9x8] - Blame information for rev 2