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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [latch/] [tb_latch.s] - Blame information for rev 2

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; Copyright 2012, Sinclair R.F., Inc.
;
; Test bench for latch peripheral.
 
.main
 
  ${3-1} :loop
 
    ; test 9-bit latch
    O_9LATCH outport
 
    1 .outport(O_9ADDR) .inport(I_9READ) .outport(O_TEST)
 
    ; test 24-bit latch
    O_24LATCH outport
 
    1 .outport(O_24ADDR) .inport(I_24READ) .outport(O_TEST)
    2 .outport(O_24ADDR) .inport(I_24READ) .outport(O_TEST)
 
    .jumpc(loop,1-) drop
 
  ; end of test
  1 .outport(O_DONE)
  :infinite .jump(infinite)

Line No.	Rev	Author	Line
1	2	sinclairrf	`; Copyright 2012, Sinclair R.F., Inc.`
2			`;`
3			`; Test bench for latch peripheral.`
4
5			`.main`
6
7			`${3-1} :loop`
8
9			`; test 9-bit latch`
10			`O_9LATCH outport`
11
12			`1 .outport(O_9ADDR) .inport(I_9READ) .outport(O_TEST)`
13
14			`; test 24-bit latch`
15			`O_24LATCH outport`
16
17			`1 .outport(O_24ADDR) .inport(I_24READ) .outport(O_TEST)`
18			`2 .outport(O_24ADDR) .inport(I_24READ) .outport(O_TEST)`
19
20			`.jumpc(loop,1-) drop`
21
22			`; end of test`
23			`1 .outport(O_DONE)`
24			`:infinite .jump(infinite)`

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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [latch/] [tb_latch.s] - Blame information for rev 2