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/*******************************************************************************

 *

 * Copyright 2012, Sinclair R.F., Inc.

 *

 * Test bench for the open_drain peripheral.

 *

 ******************************************************************************/

`timescale 1ns/1ps

module tb;

//

// 100 MHz clock and synchronous reset.

//

reg s_clk = 1'b1;

always @ (s_clk)

  s_clk <= #5 ~s_clk;

reg s_rst = 1'b1;

initial begin

  repeat (5) @ (posedge s_clk);

  s_rst = 1'b0;

end

wire s_env;

tri1 [@WIDTH@-1:0] s_od;

tb_open_drain uut(

  // synchronous reset and processor clock

  .i_rst        (s_rst),

  .i_clk        (s_clk),

  .o_env        (s_env),

  .io_od        (s_od)

);

initial begin

  repeat (100) @ (posedge s_clk);

  $finish;

end

always @ (posedge s_clk)

  $display("%12d : %b %b", $time, s_env, s_od);

endmodule