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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [servo_motor/] [tb_servo_motor.9x8] - Blame information for rev 9

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Line No. Rev Author Line
1 9 sinclairrf
#
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# Copyright 2015, Sinclair R.F., Inc.
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#
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# Test bench for servo_motor peripheral.
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#
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ARCHITECTURE    core/9x8 Verilog
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ASSEMBLY        tb_servo_motor.s
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INSTRUCTION     256
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DATA_STACK      16
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RETURN_STACK    16
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CONSTANT        C_CLK_FREQ_HZ   8_000_000
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PORTCOMMENT     3 linked servo motor
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PERIPHERAL      servo_motor     outport=O_triple_0      \
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                                outsignal=o_triple_0    \
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                                freq_hz=C_CLK_FREQ_HZ   \
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                                min_width=1000us        \
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                                max_width=1500us        \
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                                default_width=1250us    \
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                                period=5ms              \
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                                inperiod=I_triple
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PERIPHERAL      servo_motor     outport=O_triple_1      \
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                                outsignal=o_triple_1    \
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                                freq_hz=C_CLK_FREQ_HZ   \
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                                min_width=1000us        \
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                                max_width=1500us        \
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                                sync=o_triple_0
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PERIPHERAL      servo_motor     outport=O_triple_2      \
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                                outsignal=o_triple_2    \
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                                freq_hz=C_CLK_FREQ_HZ   \
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                                min_width=1000us        \
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                                max_width=1500us        \
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                                sync=o_triple_0
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PORTCOMMENT program termination
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OUTPORT 1-bit o_done O_DONE

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