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#

# Copyright 2015, Sinclair R.F., Inc.

#

# Test bench for stepper_motor peripheral.

#

ARCHITECTURE    core/9x8 Verilog

ASSEMBLY        tb_stepper_motor.s

INSTRUCTION     256

DATA_STACK      16

RETURN_STACK    16

CONSTANT        C_CLK_FREQ_HZ   2_000_000

PORTCOMMENT     stepper motor controls

CONSTANT        C_RATE_SCALE    3

CONSTANT        C_RATE_RES      16

CONSTANT        C_ACCEL_SCALE   22

CONSTANT        C_ACCEL_RES     34

CONSTANT        C_ACCUM_RES     34

CONSTANT        C_COUNT_WIDTH   19

PERIPHERAL      stepper_motor   basename=stepper                        \

                                outcontrol=O_CONTROLWORD                \

                                outrecord=O_CONTROLWORD_WR              \

                                outrun=O_GO                             \

                                indone=I_DONE                           \

                                inerror=I_ERROR                         \

                                ratemethod=C_CLK_FREQ_HZ/500_000        \

                                ratescale=C_RATE_SCALE                  \

                                rateres=C_RATE_RES                      \

                                accelscale=C_ACCEL_SCALE                \

                                accelres=C_ACCEL_RES                    \

                                accumres=C_ACCUM_RES                    \

                                countwidth=C_COUNT_WIDTH

PORTCOMMENT     program termination

OUTPORT         1-bit           o_done          O_DONE