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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [timer/] [tb_timer.9x8] - Blame information for rev 2

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#
# Copyright 2013, Sinclair R.F., Inc.
#
# Test bench for timer peripheral.
#
 
ARCHITECTURE    core/9x8 Verilog
INSTRUCTION     64
DATA_STACK      16
RETURN_STACK    16
 
PARAMETER       G_CLK_FREQ_HZ   14_745_600
PARAMETER       G_BAUD          230400
 
PERIPHERAL      timer           inport=I_TIMER_0 ratemethod=G_CLK_FREQ_HZ/G_BAUD
 
PERIPHERAL      timer           inport=I_TIMER_1 ratemethod=G_CLK_FREQ_HZ/28800
 
PERIPHERAL      timer           inport=I_TIMER_2 ratemethod=G_CLK_FREQ_HZ/1000
 
PERIPHERAL      timer           inport=I_TIMER_3 ratemethod=10_000
 
OUTPORT 2-bit,strobe o_event,o_event_wr O_EVENT
OUTPORT 1-bit o_done  O_DONE
 
ASSEMBLY tb_timer.s

Line No.	Rev	Author	Line
1	2	sinclairrf	`#`
2			`# Copyright 2013, Sinclair R.F., Inc.`
3			`#`
4			`# Test bench for timer peripheral.`
5			`#`
6
7			`ARCHITECTURE core/9x8 Verilog`
8			`INSTRUCTION 64`
9			`DATA_STACK 16`
10			`RETURN_STACK 16`
11
12			`PARAMETER G_CLK_FREQ_HZ 14_745_600`
13			`PARAMETER G_BAUD 230400`
14
15			`PERIPHERAL timer inport=I_TIMER_0 ratemethod=G_CLK_FREQ_HZ/G_BAUD`
16
17			`PERIPHERAL timer inport=I_TIMER_1 ratemethod=G_CLK_FREQ_HZ/28800`
18
19			`PERIPHERAL timer inport=I_TIMER_2 ratemethod=G_CLK_FREQ_HZ/1000`
20
21			`PERIPHERAL timer inport=I_TIMER_3 ratemethod=10_000`
22
23			`OUTPORT 2-bit,strobe o_event,o_event_wr O_EVENT`
24			`OUTPORT 1-bit o_done O_DONE`
25
26			`ASSEMBLY tb_timer.s`

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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [timer/] [tb_timer.9x8] - Blame information for rev 2