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################################################################################
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#
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# Copyright 2013-2014, Sinclair R.F., Inc.
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sinclairrf |
#
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################################################################################
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import re;
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from ssbccPeripheral import SSBCCperipheral
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from ssbccUtil import SSBCCException;
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class timer(SSBCCperipheral):
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"""
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Simple timer to facilitate polled-loops.\n
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The timer sets a flag when the timer expires and clears the flag when it is
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read.\n
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Usage:
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PERIPHERAL timer inport=I_name \\
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ratemethod={clk/rate|count}\n
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Where:
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inport=I_name
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specifies the symbol used by the inport instruction to get the
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unexpired/expired status of the timer
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Note: The name must start with "I_"
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ratemethod
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specifies the method to generate the desired timer event rate:
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1st method: clk/rate
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clk is the frequency of "i_clk" in Hz
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a number will be interpreted as the clock frequency in Hz
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a symbol will be interpreted as a constant or a parameter
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Note: the symbol must be declared with the CONSTANT, LOCALPARARM,
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or PARAMETER configuration command.
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rate is the desired baud rate
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this is specified as per "clk"
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2nd method:
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specify the number of "i_clk" clock cycles between timer events
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Note: clk, rate, and count can be parameters or constants. For example,
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the following uses the parameter G_CLK_FREQ_HZ for the clock
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frequency and a hard-wired event rate of 1 kHz
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"baudmethod=G_CLK_FREQ_HZ/1000".
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Note: The numeric values can have Verilog-style '_' separators between
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the digits. For example, 100_000_000 represents 100 million.\n
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Example: Configure the timer for 1000 kHz events and monitor for these events
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in the micro controller code.\n
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PARAMETER G_CLK_FREQ_HZ 100_000_000
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PERIPHERAL timer inport=I_TIMER ratemethod=G_CLK_FREQ_HZ/1000\n
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; See if the timer has expired since the last time it was polled and
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; conditionally call "timer_event" if it has.
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.inport(I_TIMER)
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.callc(timer_event)
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"""
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def __init__(self,peripheralFile,config,param_list,loc):
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# Use the externally provided file name for the peripheral
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self.peripheralFile = peripheralFile;
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# Get the parameters.
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allowables = (
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('inport', r'I_\w+$', None, ),
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('ratemethod', r'\S+$', lambda v : self.RateMethod(config,v), ),
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);
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names = [a[0] for a in allowables];
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for param_tuple in param_list:
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param = param_tuple[0];
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if param not in names:
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raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
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param_test = allowables[names.index(param)];
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self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
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# Ensure the required parameters are provided.
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for paramname in names:
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if not hasattr(self,paramname):
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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name = 's__%s__expired' % self.inport;
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config.AddSignal(name, 1, loc);
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config.AddSignal('s_SETRESET_%s' % name,1,loc);
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config.AddInport((self.inport,
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('s__%s__expired' % self.inport, 1, 'set-reset'),
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),loc);
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# Add the 'clog2' function to the processor (if required).
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config.functions['clog2'] = True;
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def GenVerilog(self,fp,config):
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body = self.LoadCore(self.peripheralFile,'.v');
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for subs in (
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( r'\bL__', 'L__@NAME@__', ),
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( r'\bs__', 's__@NAME@__', ),
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( r'@RATEMETHOD@', str(self.ratemethod), ),
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( r'@NAME@', self.inport, ),
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) :
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body = re.sub(subs[0],subs[1],body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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