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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [trace.py] - Blame information for rev 7

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1 2 sinclairrf
################################################################################
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#
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# Copyright 2012-2013, Sinclair R.F., Inc.
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#
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################################################################################
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import re
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from ssbccPeripheral import SSBCCperipheral
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from ssbccUtil import SSBCCException;
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class trace(SSBCCperipheral):
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  """
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  Generate a human readable printout of the processor execution.  The program
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  counter and opcode are delayed so that they are aligned with the results of
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  the opcode.\n
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  Usage:
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    PERIPHERAL trace\n
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  The following values are displayed in this order during the execution:
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    program counter
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    numeric opcode
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    human-readable opcode
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    ':'
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    data stack pointer
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    next-to-top of the data stack
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    top of the data stack
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    ':'
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    top of the return stack
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    return stack pointer\n
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  Example:  See core/9x8/tb/core which is used to validate correct operation of
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            the core.
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  """
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  def __init__(self,peripheralFile,config,params,loc):
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    # Use the externally provided file name for the peripheral
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    self.peripheralFile = peripheralFile;
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    config.functions['display_trace'] = True;
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  def GenVerilog(self,fp,config):
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    body = """
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//
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// Trace peripheral
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//
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generate
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reg [C_PC_WIDTH-1:0] s__PC_s[1:0];
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reg            [8:0] s__opcode_s = 9'h000;
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reg        [7*8-1:0] s__opcode_name;
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initial begin
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  s__PC_s[0] = {(C_PC_WIDTH){1'b0}};
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  s__PC_s[1] = {(C_PC_WIDTH){1'b0}};
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end
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always @ (posedge i_clk) begin
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  s__PC_s[0] <= s_PC;
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  s__PC_s[1] <= s__PC_s[0];
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  s__opcode_s <= s_opcode;
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  display_trace({ s__PC_s[1], s__opcode_s, s_Np_stack_ptr, 1'b1, s_N, 1'b1, s_T, 1'b1, s_R, s_R_stack_ptr });
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end
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endgenerate
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""";
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    body = re.sub(r'\bs__','s__trace__',body);
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    fp.write(body);

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