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sinclairrf |
################################################################################
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#
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# Copyright 2014, Sinclair R.F., Inc.
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#
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################################################################################
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import re;
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from ssbccPeripheral import SSBCCperipheral
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from ssbccUtil import SSBCCException;
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class wide_strobe(SSBCCperipheral):
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"""
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Generate more than one simultaneous strobe.\n
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Usage:
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PERIPHERAL wide_strobe \\
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outport=O_name \\
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outsignal=o_name \\
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width=<N>\n
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Where:
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outport=O_name
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specifies the symbol used to write to the output port
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outsignal=o_name
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specifies the name of the signal output from the module
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width=<N>
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specifies the width of the I/O
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Note: N must be between 1 and 8 inclusive.\n
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Example: Generate up to 4 simultaneous strobes.\n
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PORTCOMMENT 4 bit wide strobe
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PERIPHERAL wide_strobe \\
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outport=O_4BIT_STROBE \\
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outsignal=o_4bit_strobe \\
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width=4\n
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Send strobes on bits 1 and 3 of the wide strobe as follows:\n
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${2**1|2**3} .outport(O_4BIT_STROBE)
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"""
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def __init__(self,peripheralFile,config,param_list,loc):
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# Get the parameters.
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allowables = (
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sinclairrf |
( 'outport', r'O_\w+$', None, ),
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( 'outsignal', r'o_\w+$', None, ),
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( 'width', r'(9|[1-9]\d*)$', int, ),
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sinclairrf |
);
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names = [a[0] for a in allowables];
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for param_tuple in param_list:
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param = param_tuple[0];
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if param not in names:
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raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
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param_test = allowables[names.index(param)];
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self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
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# Ensure the required parameters are provided (all parameters are required).
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for paramname in names:
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if not hasattr(self,paramname):
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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# There are no optional parameters.
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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config.AddIO(self.outsignal,self.width,'output',loc);
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self.ix_outport = config.NOutports();
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config.AddOutport((self.outport,False,
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# empty list
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),
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loc);
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def GenVerilog(self,fp,config):
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body = """//
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// PERIPHERAL wide_strobe: @NAME@
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//
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initial @NAME@ = @WIDTH@'d0;
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always @ (posedge i_clk)
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if (i_rst)
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@NAME@ <= @WIDTH@'d0;
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else if (s_outport && (s_T == @IX_OUTPORT@))
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@NAME@ <= s_N[0+:@WIDTH@];
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else
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@NAME@ <= @WIDTH@'d0;
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"""
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for subpair in (
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sinclairrf |
( r'@IX_OUTPORT@', "8'd%d" % self.ix_outport, ),
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( r'@WIDTH@', str(self.width), ),
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( r'@NAME@', self.outsignal, ),
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):
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sinclairrf |
body = re.sub(subpair[0],subpair[1],body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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