Subversion Repositories ssbcc

################################################################################

#

# Copyright 2012-2015, Sinclair R.F., Inc.

#

# Verilog generation functions.

#

################################################################################

import math

import os

import random

import re

from ssbccUtil import *;

################################################################################

#

# Generate input and output core names.

#

################################################################################

def doFillCommand(fillCommand,fpOutCore,config):

  """

  Do core-specific fill commands for the "..@SSBCC@ <fillCommand>" lines.

  """

  # functions and tasks

  if fillCommand == "functions":

    genFunctions(fpOutCore,config);

  # inports

  elif fillCommand == 'inports':

    genInports(fpOutCore,config);

  # interrupt conditionals

  elif fillCommand == 'interrupt__s_math_rotate':

    if config.InterruptVector():

      fpOutCore.write("""  if (s_interrupt || s_interrupted)

    s_math_rotate = s_T;

  else""");

  elif fillCommand == 'interrupt__s_opcode':

    if config.InterruptVector():

      fpOutCore.write("""  if (s_interrupted) begin

    // nop

  end else if (s_interrupt) begin

    s_return    = C_RETURN_INC;

  end else""");

  # localparam

  elif fillCommand == 'localparam':

    genLocalParam(fpOutCore,config);

  # module

  elif fillCommand == 'module':

    genModule(fpOutCore,config);

  # outports

  elif fillCommand == 'outports':

    genOutports(fpOutCore,config);

  # "s_PC_next" body

  elif fillCommand == 's_PC_next':

    genSPCnext(fpOutCore,config);

  # "s_R_pre" body

  elif fillCommand == 's_R_pre':

    genSRpre(fpOutCore,config);

  # additional signals

  elif fillCommand == 'signals':

    genSignals(fpOutCore,config);

  # error

  else:

    print 'WARNING:  Unimplemented command ' + fillCommand;

def genCoreName():

  """

  Return the name of the file to use for the processor core.

  """

  return 'core.v';

def genOutName(rootName):

  """

  Return the name for the output micro controller module.

  """

  if re.match('.*\.v$',rootName):

    return rootName;

  else:

    return ("%s.v" % rootName);

################################################################################

#

# Generate the code to run the INPORT selection, the associated output

# strobes,and the set-reset latches.

#

################################################################################

def genFunctions(fp,config):

  """

  Output the optional bodies for the following functions and tasks:

    clog2               when $clog2 isn't available by commanding "--define_clog2"

                        on the ssbcc command line

    display_opcode      human-readable version of the opcode suitable for

                        waveform viewers

    display_trace       when the trace or monitor_stack peripherals are included

  """

  def DisableInterrupt(body):

    for replace in ('s_interrupt','s_interrupted',):

      replace = '\(' + replace + '\)';

      while re.search(replace,body):

        body = re.sub(replace,'(1\'b0)',body);

    return body;

  if 'display_opcode' in config.functions:

    displayOpcodePath = os.path.join(config.Get('corepath'),'display_opcode.v');

    fpDisplayOpcode = open(displayOpcodePath,'rt');

    if not fpDisplayOpcode:

      raise Exception('Program Bug -- "%s" not found' % displayOpcodePath);

    body = fpDisplayOpcode.read();

    fpDisplayOpcode.close();

    if not config.InterruptVector():

      body = DisableInterrupt(body);

    fp.write(body);

  if ('clog2' in config.functions) and config.Get('define_clog2'):

    fp.write("""

// Use constant function instead of builtin $clog2.

function integer clog2;

  input integer value;

  integer temp;

  begin

    temp = value - 1;

    for (clog2=0; temp>0; clog2=clog2+1)

      temp = temp >> 1;

  end

endfunction

""");

  if 'display_trace' in config.functions:

    displayTracePath = os.path.join(config.Get('corepath'),'display_trace.v');

    fpDisplayTrace = open(displayTracePath,'rt');

    if not fpDisplayTrace:

      raise Exception('Program Bug -- "%s" not found' % displayTracePath);

    body = fpDisplayTrace.read();

    fpDisplayTrace.close();

    if not config.InterruptVector():

      body = DisableInterrupt(body);

    fp.write(body);

def genInports(fp,config):

  """

  Generate the logic for the input signals.

  """

  if not config.inports:

    fp.write('// no input ports\n');

    return

  haveBitInportSignals = False;

  for ix in range(config.NInports()):

    thisPort = config.inports[ix][1:];

    for jx in range(len(thisPort)):

      signal = thisPort[jx];

      signalType = signal[2];

      if signalType in ('data','set-reset',):

        haveBitInportSignals = True;

  if haveBitInportSignals:

    fp.write('always @ (*)\n');

    fp.write('  case (s_T)\n');

  for ix in range(config.NInports()):

    thisPort = config.inports[ix][1:];

    nbits = 0;

    bitString = '';

    for jx in range(len(thisPort)):

      signal = thisPort[jx];

      signalName = signal[0];

      signalSize = signal[1];

      signalType = signal[2];

      if signalType == 'data':

        nbits = nbits + signalSize;

        if len(bitString)>0:

          bitString += ', ';

        bitString = bitString + signalName;

      if signalType == 'set-reset':

        fp.write('      8\'h%02X : s_T_inport = (%s || s_SETRESET_%s) ? 8\'hFF : 8\'h00;\n' % (ix, signalName, signalName));

    if nbits == 0:

      pass;

    elif nbits < 8:

      fp.write('      8\'h%02X : s_T_inport = { %d\'h0, %s };\n' % (ix,8-nbits,bitString));

    elif nbits == 8:

      fp.write('      8\'h%02X : s_T_inport = %s;\n' % (ix,bitString));

    else:

      fp.write('      8\'h%02X : s_T_inport = %s[0+:8];\n' % (ix,bitString));

  if haveBitInportSignals:

    fp.write('    default : s_T_inport = 8\'h00;\n');

    fp.write('  endcase\n');

    fp.write('\n');

  # Generate all the INPORT strobes.

  for ix in range(config.NInports()):

    thisPort = config.inports[ix][1:];

    for jx in range(len(thisPort)):

      signal = thisPort[jx];

      signalName = signal[0];

      signalType = signal[2];

      if signalType == 'strobe':

        fp.write('always @ (posedge i_clk)\n');

        fp.write('  if (i_rst)\n');

        fp.write('    %s <= 1\'b0;\n' % signalName);

        fp.write('  else if (s_inport)\n');

        fp.write('    %s <= (s_T == 8\'h%02X);\n' % (signalName,ix));

        fp.write('  else\n');

        fp.write('    %s <= 1\'b0;\n' % signalName);

        fp.write('\n');

  # Generate all the INPORT "set-reset"s.

  for ix in range(config.NInports()):

    thisPort = config.inports[ix][1:];

    if thisPort[0][2] == 'set-reset':

      signalName = thisPort[0][0];

      fp.write('always @(posedge i_clk)\n');

      fp.write('  if (i_rst)\n');

      fp.write('    s_SETRESET_%s <= 1\'b0;\n' % signalName);

      fp.write('  else if (s_inport && (s_T == 8\'h%02X))\n' % ix);

      fp.write('    s_SETRESET_%s <= 1\'b0;\n' % signalName);

      fp.write('  else if (%s)\n' % signalName);

      fp.write('    s_SETRESET_%s <= 1\'b1;\n' % signalName);

      fp.write('  else\n');

      fp.write('    s_SETRESET_%s <= s_SETRESET_%s;\n' % (signalName,signalName));

def genLocalParam(fp,config):

  """

  Generate the localparams for implementation-specific constants.

  """

  pcWidth = CeilLog2(config.Get('nInstructions')['length']);

  fp.write('localparam C_PC_WIDTH                              = %4d;\n' % pcWidth);

  fp.write('localparam C_RETURN_PTR_WIDTH                      = %4d;\n' % CeilLog2(config.Get('return_stack')));

  fp.write('localparam C_DATA_PTR_WIDTH                        = %4d;\n' % CeilLog2(config.Get('data_stack')));

  fp.write('localparam C_RETURN_WIDTH                          = (C_PC_WIDTH <= 8) ? 8 : C_PC_WIDTH;\n');

def genMemories(fp,fpMemFile,config,programBody):

  """

  Generate the memories for the instructions, data stack, return stack, and the

  memories and the operations to access these memories in this order.

  Initialize the instruction memory.\n

  fp            file handle for the output core

  fpMemFile     file handle for the memory initialization file

                Note:  This can be used to avoid running synthesis again.

  """

  combines = config.config['combine'];

  # Declare instruction ROM(s).

  instructionMemory = config.Get('nInstructions');

  instructionAddrWidth = (instructionMemory['nbits_blockSize']+3)/4;

  instructionNameIndexWidth = (instructionMemory['nbits_nBlocks']+3)/4;

  instructionMemNameFormat = 's_opcodeMemory_%%0%dX' % instructionNameIndexWidth;

  (combined,port,packing) = config.GetPacking('INSTRUCTION');

  instruction_mem_width = combined['memWidth'];

  for ixBlock in range(instructionMemory['nBlocks']):

    if instructionMemory['nBlocks'] == 1:

      memName = 's_opcodeMemory';

    else:

      memName = instructionMemNameFormat % ixBlock;

    if config.Get('synth_instr_mem'):

      fp.write('%s ' % config.Get('synth_instr_mem'));

    fp.write('reg [%d:0] %s[%d:0];\n' % (instruction_mem_width-1,memName,instructionMemory['blockSize']-1,));

  # Declare data stack RAM and return stacks RAM if they aren't combined into other memories.

  for memType in ('DATA_STACK','RETURN_STACK',):

    (combined,port,packing) = config.GetPacking(memType);

    if combined['port'][0]['packing'][0]['name'] != memType:

      continue;

    fp.write('reg [%d:0] %s[%d:0];\n' % (combined['memWidth']-1,combined['memName'],combined['nWords']-1,));

  # Declare the memories.

  for combined in combines:

    if combined['mems'][0] in ('INSTRUCTION','DATA_STACK','RETURN_STACK',):

      continue;

    fp.write('reg [%d:0] %s[%d:0];\n' % (combined['memWidth']-1,combined['memName'],combined['nWords']-1,));

  # Vertical separation between declarations and first initialization.

  fp.write('\n');

  # Initialize the instruction memory.

  (combined,port,packing) = config.GetPacking('INSTRUCTION');

  fp.write('initial begin\n');

  ixRecordedBody = 0;

  nbits = combined['memWidth'];

  ixInstruction = 0;

  instructionBodyLength = packing['length'];

  for ixBlock in range(instructionMemory['nBlocks']):

    if instructionMemory['nBlocks'] == 1:

      memName = 's_opcodeMemory';

    else:

      memName = instructionMemNameFormat % ixBlock;

    if nbits == 9:

      formatp = '  %s[\'h%%0%dX] = { 1\'b1, %%s };' % (memName,instructionAddrWidth,);

      formatn = '  %s[\'h%%0%dX] = 9\'h%%s; // %%s\n' % (memName,instructionAddrWidth,);

      formate = '  %s[\'h%%0%dX] = 9\'h%%03x;\n' % (memName,instructionAddrWidth,);

    else:

      formatp = '  %s[\'h%%0%dX] = { %d\'d0, 1\'b1, %%s };' % (memName,instructionAddrWidth,nbits-9,);

      formatn = '  %s[\'h%%0%dX] = { %d\'d0, 9\'h%%s }; // %%s\n' % (memName,instructionAddrWidth,nbits-9,);

      formate = '  %s[\'h%%0%dX] = { %d\'d0, 9\'h%%03x };\n' % (memName,instructionAddrWidth,nbits-9,);

    rand_instr_mem = config.Get('rand_instr_mem');

    for ixMem in range(instructionMemory['blockSize']):

      memAddr = instructionMemory['blockSize']*ixBlock+ixMem;

      if ixRecordedBody < len(programBody):

        for ixRecordedBody in range(ixRecordedBody,len(programBody)):

          if programBody[ixRecordedBody][0] == '-':

            fp.write('  // %s\n' % programBody[ixRecordedBody][2:]);

          else:

            if programBody[ixRecordedBody][0] == 'p':

              (parameterString,parameterComment) = re.findall(r'(\S+)(.*)$',programBody[ixRecordedBody][2:])[0];

              fp.write(formatp % (ixMem,parameterString,));

              fpMemFile.write('@%04X %03X\n' % (memAddr,0x100 + config.GetParameterValue(parameterString)));

              if len(parameterComment) > 0:

                fp.write(' // %s' % parameterComment[1:]);

              fp.write('\n');

            else:

              fp.write(formatn % (ixMem,programBody[ixRecordedBody][0:3],programBody[ixRecordedBody][4:]));

              fpMemFile.write('@%04X %s\n' % (memAddr,programBody[ixRecordedBody][0:3],));

            break;

        ixRecordedBody = ixRecordedBody + 1;

      elif ixInstruction < instructionBodyLength:

        fp.write(formate % (ixMem,0 if not rand_instr_mem else random.randint(0,2**9-1),));

        fpMemFile.write('@%04X 000\n' % memAddr);

      else:

        break;

      ixInstruction = ixInstruction + 1;

    # Save the last memory name for memories combined at the end of the instruction memory.

    combined['memName'] = memName;

  if len(combined['port']) > 1:

    offset0 = instructionMemory['blockSize']*(instructionMemory['nBlocks']-1);

    combined['port'][1]['offset'] -= offset0;

    genMemories_init(fp,config,combined,fpMemFile=fpMemFile,memName=memName,memLength=instructionMemory['blockSize']);

  fp.write('end\n\n');

  # Initialize the data stack.

  for combined in [thisCombined for thisCombined in combines if thisCombined['port'][0]['packing'][0]['name'] == 'DATA_STACK']:

    fp.write('initial begin\n');

    genMemories_init(fp,config,combined);

    fp.write('end\n\n');

    break;

  # Initialize the return stack.

  for combined in [thisCombined for thisCombined in combines if thisCombined['port'][0]['packing'][0]['name'] == 'RETURN_STACK']:

    fp.write('initial begin\n');

    genMemories_init(fp,config,combined);

    fp.write('end\n\n');

    break;

  # Initialize the memories

  for combined in [thisCombined for thisCombined in combines if thisCombined['port'][0]['packing'][0]['name'] not in ('INSTRUCTION','DATA_STACK','RETURN_STACK',)]:

    fp.write('initial begin\n');

    genMemories_init(fp,config,combined);

    fp.write('end\n\n');

  # Generate the opcode read logic.

  fp.write('//\n');

  fp.write('// opcode read logic\n');

  fp.write('//\n');

  fp.write('\n');

  fp.write('initial s_opcode = 9\'h000;\n');

  if instruction_mem_width == 10:

    fp.write('reg not_used_s_opcode = 1\'b0;\n');

  elif instruction_mem_width > 10:

    fp.write('reg [%d:0] not_used_s_opcode = %d\'d0;\n' % (instruction_mem_width-10,instruction_mem_width-9,));

  fp.write('always @ (posedge i_clk)\n');

  fp.write('  if (i_rst) begin\n');

  fp.write('    s_opcode <= 9\'h000;\n');

  if instruction_mem_width > 9:

    fp.write('    not_used_s_opcode <= %d\'d0;\n' % (instruction_mem_width-9,));

  if instruction_mem_width == 9:

    instructionReadTarget = 's_opcode';

  else:

    instructionReadTarget = '{ not_used_s_opcode, s_opcode }';

  if instructionMemory['nBlocks'] == 1:

    fp.write('  end else\n');

    fp.write('    %s <= s_opcodeMemory[s_PC];\n' % instructionReadTarget);

  else:

    fp.write('  end else case (s_PC[%d+:%d])\n' % (instructionMemory['nbits_blockSize'],instructionMemory['nbits_nBlocks'],));

    for ixBlock in range(instructionMemory['nBlocks']):

      memName = instructionMemNameFormat % ixBlock;

      thisLine = '%d\'h%X : %s <= %s[s_PC[0+:%d]];\n' % (instructionMemory['nbits_nBlocks'],ixBlock,instructionReadTarget,memName,instructionMemory['nbits_blockSize'],);

      while thisLine.index(':') < 12:

        thisLine = ' ' + thisLine;

      fp.write(thisLine);

    fp.write('    default : %s <= %d\'h000;\n' % (instructionReadTarget,instruction_mem_width,));

    fp.write('  endcase\n');

  fp.write('\n');

  #

  # Generate the data_stack read and write logic.

  #

  fp.write('//\n// data stack read and write logic\n//\n\n');

  (combined,port,packing) = config.GetPacking('DATA_STACK');

  genMemories_stack(fp,combined,port,packing,'s_N','s_Np','s_stack == C_STACK_INC');

  #

  # Generate the return_stack read and write logic.

  #

  fp.write('//\n// return stack read and write logic\n//\n\n');

  (combined,port,packing) = config.GetPacking('RETURN_STACK');

  genMemories_stack(fp,combined,port,packing,'s_R_pre','s_R','s_return == C_RETURN_INC');

  #

  # Coalesce the memory bank indices and the corresponding memory names, offsets, lengths, etc.

  #

  lclMemName = [];

  lclMemParam = [];

  for ixBank in range(4):

    memParam = config.GetMemoryByBank(ixBank);

    if not memParam:

      continue;

    lclMemName.append(memParam['name']);

    lclMemParam.append(dict(bank=memParam['bank'],type=memParam['type']));

  for combined in combines:

    for port in combined['port']:

      if port['packing'][0]['name'] in ('INSTRUCTION','DATA_STACK','RETURN_STACK',):

        continue;

      for packing in port['packing']:

        if packing['name'] not in lclMemName:

          print 'WARNING:  Memory "%s" not used in program' % packing['name'];

          continue;

        ixLclMem = lclMemName.index(packing['name']);

        thisLclMemParam = lclMemParam[ixLclMem];

        thisLclMemParam['combined'] = combined;

        thisLclMemParam['port'] = port;

        thisLclMemParam['packing'] = packing;

  # Generate the memory read/write logic.

  if config.NMemories() == 0:

    fp.write('// no memories\n\n');

  else:

    # Compute the address string / address string format for each RAM/ROM port.

    for combined in combines:

      for port in combined['port']:

        addrWidth = CeilLog2(port['nWords'])-CeilLog2(port['ratio']);

        addrString = '';

        if len(combined['port']) > 1:

          addrString = '{' + addrString;

          nMajorAddressBits = CeilLog2(combined['nWords']) - CeilLog2(port['nWords']);

          addrString += '%d\'h%x,' % (nMajorAddressBits,port['offset']/port['nWords'],);

        addrString += 's_T[%d:0]' % (addrWidth-1,);

        if port['ratio'] > 1:

          if '{' not in addrString:

            addrString = '{' + addrString;

          addrString += ',%d\'d%%d' % (CeilLog2(port['ratio']),);

        if '{' in addrString:

          addrString += '}';

        port['addrString'] = addrString;

    # Generate the memory read logic.

    fp.write('//\n// memory read logic\n//\n\n');

    for combined in combines:

      if combined['memArch'] != 'sync':

        continue;

      memName = combined['memName'];

      memWidth = combined['memWidth'];

      for port in combined['port']:

        if port['packing'][0]['name'] in ('INSTRUCTION','DATA_STACK','RETURN_STACK',):

          continue;

        addrString = port['addrString'];

        totalWidth = memWidth * port['ratio'];

        if combined['memArch'] == 'sync':

          fp.write('reg [%d:0] %s_reg = %d\'h0;\n' % (totalWidth-1,memName,totalWidth,));

        if port['ratio'] == 1:

          fp.write('always @ (%s[%s])\n' % (memName,addrString,));

          fp.write('  %s_reg = %s[%s];\n' % (memName,memName,addrString,));

        else:

          fp.write('always @ (');

          for ratio in range(port['ratio']):

            if ratio != 0:

              fp.write(',');

            fp.write('%s[%s]' % (memName,(addrString % ratio),));

          fp.write(') begin\n');

          for ratio in range(port['ratio']):

            fp.write('  %s_reg[%d+:%d] = %s[%s];\n' % (memName,ratio*memWidth,memWidth,memName,(addrString % ratio),));

          fp.write('end\n');

    for ixLclMemParam in range(len(lclMemParam)):

      thisLclMemParam = lclMemParam[ixLclMemParam];

      combined = thisLclMemParam['combined'];

      if ixLclMemParam == 0:

        fp.write('assign s_memory = ');

      else:

        fp.write('                : ');

      fp.write('(s_opcode[0+:2] == 2\'d%d) ? ' % thisLclMemParam['bank']);

      if combined['memArch'] == 'LUT':

        fp.write('%s[%s]\n' % (combined['memName'],thisLclMemParam['port']['addrString'],));

      else:

        fp.write('%s_reg[%d+:8]\n' % (combined['memName'],combined['memWidth']*thisLclMemParam['packing']['lane'],));

    fp.write('                : 8\'d0;\n');

    fp.write('\n');

    # Generate the memory write logic.

    fp.write('//\n// memory write logic\n//\n\n');

    for combined in combines:

      for port in combined['port']:

        if port['packing'][0]['name'] in ('INSTRUCTION','DATA_STACK','RETURN_STACK',):

          continue;

        thisRams = [];

        for packing in port['packing']:

          memParam = config.GetMemoryByName(packing['name']);

          if not memParam:

            continue;

          if memParam['type'] != 'RAM':

            continue;

          thisRams.append({ 'memParam':memParam, 'packing':packing });

        if not thisRams:

          continue;

        fp.write('always @ (posedge i_clk) begin\n');

        for ram in thisRams:

          memParam = ram['memParam'];

          packing = ram['packing'];

          if combined['memArch'] == 'LUT':

            fp.write('  if (s_mem_wr && (s_opcode[0+:2] == 2\'d%d))\n' % memParam['bank']);

            fp.write('    %s[%s] <= s_N; // memory %s\n' % (combined['memName'],port['addrString'],packing['name'],));

          else:

            addrString = port['addrString'];

            if '%' in addrString:

              addrString = addrString % packing['lane'];

            fp.write('  if (s_mem_wr && (s_opcode[0+:2] == 2\'d%d))\n' % memParam['bank']);

            if combined['memWidth'] == 8:

              source = 's_N';

            else:

              source = '{ %d\'d0, s_N }' % (combined['memWidth']-8);

            fp.write('    %s[%s] <= %s; // memory %s\n' % (combined['memName'],addrString,source,packing['name'],));

        fp.write('end\n\n');

def genMemories_assign(fp,mode,combined,port,packing,addr,sigName):

  """

  Utility function for genMemories.\n

  Generate the logic to perform memory writes, including writes to multiple

  memory locations (for the return stack) and writing zeros to otherwise unused

  bits.

  """

  if mode not in ['write','read']:

    raise Exception('Program Bug: %s' % mode);

  memName = combined['memName'];

  memWidth = combined['memWidth'];

  ratio = packing['ratio']

  sigWidth = packing['nbits'];

  nbitsRatio = CeilLog2(ratio);

  notUsedWidth = ratio*memWidth - sigWidth;

  isLUT = (combined['memArch'] == 'LUT');

  if not isLUT and port['nWords'] != combined['nWords']:

    memAddrWidth = CeilLog2(combined['nWords']);

    thisAddrWidth = CeilLog2(packing['nWords']);

    nbitsOffset = memAddrWidth - thisAddrWidth;

    addr = '{%d\'h%%0%dx,%s}' % (nbitsOffset,(nbitsOffset+3)/4,addr,) % (port['offset']/2**thisAddrWidth,);

  for ixRatio in range(ratio):

    ix0 = ixRatio*memWidth;

    ix1 = ix0+memWidth;

    if ratio == 1:

      thisAddr = addr;

    else:

      thisAddr = '%s, %d\'h%%0%dx' % (addr,nbitsRatio,(nbitsRatio+3)/4,) % ixRatio;

    if thisAddr.find(',') != -1:

      thisAddr = '{ %s }' % thisAddr;

    if ix1 <= sigWidth:

      thisSignal = '%s[%d:%d]' % (sigName,ix1-1,ix0,);

    elif ix0 <= sigWidth:

      nEmpty = ix1-sigWidth;

      if mode == 'write':

        thisSignal = '{ %d\'d0, %s[%d:%d] }' % (nEmpty,sigName,sigWidth-1,ix0,);

      elif notUsedWidth == 1:

        thisSignal = '{ not_used_%s, %s[%d:%d] }' % (sigName,sigName,sigWidth-1,ix0,);

      else:

        thisSignal = '{ not_used_%s[%d:0], %s[%d:%d] }' % (sigName,ix1-sigWidth-1,sigName,sigWidth-1,ix0,);

    else:

      if mode == 'write':

        thisSignal = '%d\'0' % memWidth;

      else:

        thisSignal = 'not_used_%s[%d:%d]' % (sigName,ix1-sigWidth-1,ix0-sigWidth,);

    if mode == 'write' and isLUT:

      fp.write('    %s[%s] <= %s;\n' % (memName,thisAddr,thisSignal,));

    elif mode == 'write' and not isLUT:

      fp.write('    %s[%s] = %s; // coerce write-through\n' % (memName,thisAddr,thisSignal,));

    elif mode == 'read' and not isLUT:

      fp.write('  %s <= %s[%s];\n' % (thisSignal,memName,thisAddr,));

    elif mode == 'read' and isLUT:

      fp.write('always @ (%s[%s],%s)\n' % (memName,thisAddr,thisAddr,));

      fp.write('  %s = %s[%s];\n' % (thisSignal,memName,thisAddr,));

def genMemories_init(fp,config,combined,fpMemFile=None,memName=None,memLength=None):

  """

  Utility function for genMemories.\n

  Generate the logic to initialize memories based on the memory width and the

  initialization output from the assembler.

  """

  if not memName:

    memName = combined['memName'];

  if not memLength:

    memLength = combined['nWords'];

  memWidth = combined['memWidth'];

  # Compute the formatting for the initialization values

  nAddrBits = CeilLog2(memLength);

  if memWidth == 8:

    formatd = '%s[\'h%%0%dX] = 8\'h%%s;' % (memName,(nAddrBits+3)/4,);