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[/] [ssbcc/] [trunk/] [core/] [9x8/] [tb/] [arch/] [arch-1r2m.9x8] - Blame information for rev 10

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################################################################################
#
# Copyright 2013, Sinclair R.F., Inc.
#
# Architecture test -- single ROM, dual RAM tests
#
################################################################################
 
ARCHITECTURE    core/9x8 Verilog
 
INSTRUCTION     2048
DATA_STACK      32
RETURN_STACK    32
@RAM_A@
@RAM_B@
@ROM_Z@
@COMBINE@
 
PORTCOMMENT simulation completed strobe
OUTPORT         strobe  o_done_strobe   O_DONE_STROBE
 
PERIPHERAL      trace
 
ASSEMBLY        arch-1r2m.s

Line No.	Rev	Author	Line
1	2	sinclairrf	`################################################################################`
2			`#`
3			`# Copyright 2013, Sinclair R.F., Inc.`
4			`#`
5			`# Architecture test -- single ROM, dual RAM tests`
6			`#`
7			`################################################################################`
8
9			`ARCHITECTURE core/9x8 Verilog`
10
11			`INSTRUCTION 2048`
12			`DATA_STACK 32`
13			`RETURN_STACK 32`
14			`@RAM_A@`
15			`@RAM_B@`
16			`@ROM_Z@`
17			`@COMBINE@`
18
19			`PORTCOMMENT simulation completed strobe`
20			`OUTPORT strobe o_done_strobe O_DONE_STROBE`
21
22			`PERIPHERAL trace`
23
24			`ASSEMBLY arch-1r2m.s`

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[/] [ssbcc/] [trunk/] [core/] [9x8/] [tb/] [arch/] [arch-1r2m.9x8] - Blame information for rev 10