URL https://opencores.org/ocsvn/ssbcc/ssbcc/trunk

Subversion Repositories ssbcc

[/] [ssbcc/] [trunk/] [core/] [9x8/] [tb/] [arch/] [arch-1rom.9x8] - Blame information for rev 9

Go to most recent revision | Details | Compare with Previous | View Log


################################################################################
#
# Copyright 2013, Sinclair R.F., Inc.
#
# Architecture test -- single ROM tests
#
################################################################################
 
ARCHITECTURE    core/9x8 Verilog
 
INSTRUCTION     2048
DATA_STACK      32
RETURN_STACK    32
@ROM_Z@
@COMBINE@
 
PORTCOMMENT simulation completed strobe
OUTPORT         strobe  o_done_strobe   O_DONE_STROBE
 
PERIPHERAL      trace
 
ASSEMBLY        arch-1rom.s

Line No.	Rev	Author	Line
1	2	sinclairrf	`################################################################################`
2			`#`
3			`# Copyright 2013, Sinclair R.F., Inc.`
4			`#`
5			`# Architecture test -- single ROM tests`
6			`#`
7			`################################################################################`
8
9			`ARCHITECTURE core/9x8 Verilog`
10
11			`INSTRUCTION 2048`
12			`DATA_STACK 32`
13			`RETURN_STACK 32`
14			`@ROM_Z@`
15			`@COMBINE@`
16
17			`PORTCOMMENT simulation completed strobe`
18			`OUTPORT strobe o_done_strobe O_DONE_STROBE`
19
20			`PERIPHERAL trace`
21
22			`ASSEMBLY arch-1rom.s`

Browse

Tools

Subversion Repositories ssbcc

[/] [ssbcc/] [trunk/] [core/] [9x8/] [tb/] [arch/] [arch-1rom.9x8] - Blame information for rev 9