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sinclairrf |
<!-- Copyright 2012, Sinclair R.F., Inc. -->
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<title>
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SSBCC -- Small Stack-Based Computer Compiler
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</title>
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<body>
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This document describes the purpose and design methodology of the Small
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Stack-Based Computer Compiler (SSBCC).<br/><br/>
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The system is designed to run a Forth-like assembly.<br/><br/>
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<h1>Introduction</h1>
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The purpose of the SSBCC is to generate small microcontrollers for use in
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FPGAs. This computer compiler is designed to generate FPGA-vendor
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independent systems in either Verilog or VHDL. The resulting micro
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controller is described by a single HDL file containing the processor core,
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the program, data stack, return stack, and variable memory.<br/><br/>
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The archive consists of the computer compiler, micro computer cores and
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assemblers, and libraries.<br/><br/>
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<h1>Processor Architecture</h1>
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TODO -- RFS: describe the general architecture<br/><br/>
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<h1>8-bit Processor Example</h1>
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This section demonstrates how to generate a 8-bit processor with 9-bit wide
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instructions. The 8-bit data width was chosen because it is characteristic
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of embedded systems controlling other processes and generating ascii output.
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The 9-bit data width was chosen because the FPGAs produced by the three
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major FPGA vendors produce memories with 8-bit data widths.<br/><br/>
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The processor is described by a regular text file with the following contents:
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<ul>
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<li>A description of the program memory, the stack memory, the return
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stack memory, the variable memory, and the I/O ports.<br/><br/>
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This part of the processor may be FPGA-dependent. For example, Altera's
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Cyclone III FPGAs do not have distributed memory, so short memories in
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those FPGAs are either extremely inefficient or are converted into an
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M9K, in which case you ought to state that an M9K is going to be used
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anyway. As another example, Xilinx' Spartan 6 has 6-input
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LUTs that can be used as distributed memory, so a 128-word program can
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be efficiently stored in 18 LUTs instead of occupying a precious
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Block RAM. Additionally, if the program is between 129 and 192 words,
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i.e., it would fit in 3 64x9 LUTs, then the program ROM can be
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described as such, saving 9 LUT in this case.<br/><br/>
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</li>
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<li>An instruction to load the processor core and its intrinsics.<br/><br/>
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This instruction loads the HDL instantiating processor core, i.e., its
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opcode interpretation, ALU, stack manipulation, etc.<br/><br/>
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This instruction also loads the list of Forth operations supported
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natively by the processor core and the instructions on how to construct
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the machine opcodes from those instructions.<br/><br/>
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For example, the '<tt>+</tt>' instruction is translated directly to the
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opcode <tt>0_XXXX_XXXX</tt>.<br/><br/>
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TODO -- RFS: fill in the "X"s above.<br/><br/>
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As another example, the 9-bit opcodes for this particular machine use
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a leading bit of '<tt>0</tt>' to indicate that an 8-bit value is to be
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pushed onto the stack. An 8-bit opcode cannot put the full range
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of 8-bit values onto the stack in a single instruction. Instead, a
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7-bit, positive value is pushed onto the stack and then, if this is
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not the desired value, an "<tt>invert</tt>" instruction immediately
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follows and is used to invert the leading bit of the of the top of the
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stack.<br/><br/>
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</li>
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<li>An optional instruction to load definitions of the remaining Forth
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instructions.<br/><br/>
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For example, a processor core could implement the Forth instructions
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"<tt>0<</tt>" and "<tt>0=</tt>" and none of the remaining
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comparison operators "<tt>0<=</tt>", "<tt>0></tt>",
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"<tt>0>=</tt>", and "<tt>0<></tt>". The optional instructions
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would include statements like:<br/><br/>
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<tt> : 0
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</li>
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</ul>
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<h1>Processor Description Syntax</h1>
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<h2>Memory Description</h2>
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<h2>
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<h1>Core Description Syntax</h1>
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<h2>Opcode List</h2>
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This section lists the opcodes and describes how the compiler is to
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implement them.<br/><br/>
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TODO -- RFS: Determine this syntax<br/><br/>
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<h2>HDL Section(s)</h2>
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Each of these sections lists the processor core implementation in the
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specified language.<br/><br/>
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The languages currently supported by the compiler are Verilog and
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VHDL.<br/><br/>
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<b>Syntax:</b> <tt>HDL {Verilog|VHDL} ... ENDHDL</tt><br/><br/>
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<b>Example:</b><br/>
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<pre>HDL Verilog
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always @ (posedge i_clk) begin
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s_stack_addr <= s_stack_addr;
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if (s_opcode[C_NBITS_OPCODE-1] = 1'b0) begin
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s_stack[s_stack_addr] <= s_opcode[C_NBITS_OPCODE-2:0];
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s_stack_addr <= s_stack_addr + 1;
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else
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end
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end
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ENDHDL
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</pre><br/>
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</body>
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</html>
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