OpenCores
URL https://opencores.org/ocsvn/ssbcc/ssbcc/trunk

Subversion Repositories ssbcc

[/] [ssbcc/] [trunk/] [example/] [hello_world/] [tb.sav] - Blame information for rev 14

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 sinclairrf
[timestart] 1131402700
2
[size] 1920 1171
3
[pos] -1 -1
4
*-15.429938 1131560000 87280000 174310000 261340000 348370000 435400000 522430000 609460000 696490000 783520000 870550000 957580000 1044610000 1131510000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
5
[treeopen] tb.
6
@800200
7
-I/Os
8
@28
9
tb.uut.i_clk
10
tb.uut.i_rst
11
tb.uut.o_UART_Tx
12
@1000200
13
-I/Os
14
@800200
15
-processor
16
@22
17
tb.uut.s_PC[4:0]
18
@23
19
tb.uut.s_opcode[8:0]
20
@22
21
tb.uut.s_Rp_ptr[4:0]
22
tb.uut.s_R[7:0]
23
tb.uut.s_T[7:0]
24
tb.uut.s_N[7:0]
25
tb.uut.s_Np_stack_ptr[4:0]
26
@1000200
27
-processor
28
@800200
29
-UART_Tx
30
@28
31
tb.uut.s_UART_wr
32
tb.uut.s_count_is_zero
33
@22
34
tb.uut.s_out_stream[7:0]
35
@28
36
tb.uut.o_UART_Tx
37
@22
38
tb.uut.s_ntx[3:0]
39
@28
40
tb.uut.s_UART_busy
41
@1000200
42
-UART_Tx
43
[pattern_trace] 1
44
[pattern_trace] 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.