OpenCores
URL https://opencores.org/ocsvn/ssbcc/ssbcc/trunk

Subversion Repositories ssbcc

[/] [ssbcc/] [trunk/] [example/] [i2c/] [TMP100/] [Xilinx-SP601/] [sp601.v] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 sinclairrf
/*******************************************************************************
2
 *
3
 * Copyright 2012, Sinclair R.F., Inc.
4
 *
5
 * Top-level module to demonstrate reading four TMP100 I2C temperature sensors
6
 * and  to display their hex outputs to a console about once per second.
7
 *
8
 ******************************************************************************/
9
 
10
module sp601(
11
  // 200 MHz differential clock
12
  input  wire   ip_sysclk_p,
13
  input  wire   ip_sysclk_n,
14
  // I2C bus
15
  inout  wire   iop_i2c_scl,
16
  inout  wire   iop_i2c_sda,
17
  // UART Tx
18
  output wire   op_usb_1_rx,
19
  // echo I2C bus to logic analyzer
20
  output wire   op_i2c_scl,
21
  output wire   op_i2c_sda
22
);
23
 
24
/*
25
 * Generate a 100 MHz clock from the 200 MHz oscillator.
26
 */
27
 
28
wire s_sysclk;
29
IBUFGDS sysclk_inst(
30
  .I    (ip_sysclk_p),
31
  .IB   (ip_sysclk_n),
32
  .O    (s_sysclk)
33
);
34
 
35
wire s_divclk;
36
BUFIO2 #(
37
  .DIVIDE               (4),
38
  .DIVIDE_BYPASS        ("FALSE"),
39
  .USE_DOUBLER          ("TRUE")
40
) bufio2_inst (
41
  .I            (s_sysclk),
42
  .IOCLK        (),
43
  .DIVCLK       (s_divclk),
44
  .SERDESSTROBE ()
45
);
46
 
47
wire s_clk;
48
BUFG sclk_inst(
49
  .I    (s_divclk),
50
  .O    (s_clk)
51
);
52
 
53
/*
54
 * Generate a synchronous reset.
55
 */
56
 
57
reg [3:0] s_reset_count = 4'hF;
58
always @ (posedge s_clk)
59
  s_reset_count <= s_reset_count - 4'd1;
60
 
61
reg s_rst = 1'b1;
62
always @ (posedge s_clk)
63
  if (s_reset_count == 4'd0)
64
    s_rst <= 1'b0;
65
  else
66
    s_rst <= s_rst;
67
 
68
/*
69
 * Instantiate the micro controller.
70
 */
71
 
72
i2c_tmp100 ie_inst(
73
  // synchronous reset and processor clock
74
  .i_rst        (s_rst),
75
  .i_clk        (s_clk),
76
  // I2C bus
77
  .io_scl       (iop_i2c_scl),
78
  .io_sda       (iop_i2c_sda),
79
  // UART_Tx port
80
  .o_UART_Tx    (op_usb_1_rx)
81
);
82
 
83
/*
84
 * Copy the I2C bus to the logic analyzer outputs.
85
 */
86
 
87
assign op_i2c_scl = iop_i2c_scl;
88
assign op_i2c_sda = iop_i2c_sda;
89
 
90
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.