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[/] [ssbcc/] [trunk/] [example/] [led/] [tb.sav] - Blame information for rev 2

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Line No. Rev Author Line
1 2 sinclairrf
[timestart] 0
2
[size] 1920 1171
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[pos] -1 -1
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*-15.852333 250000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
5
[treeopen] tb.
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[treeopen] tb.uut.
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@28
8
tb.uut.i_rst
9
tb.uut.i_clk
10
tb.uut.o_led
11
@800200
12
-critical signals
13
@22
14
tb.uut.s_PC[10:0]
15
tb.uut.s_opcode[8:0]
16
tb.uut.s_Rp_ptr[4:0]
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tb.uut.s_R[10:0]
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@28
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tb.uut.s_T_valid
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@22
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tb.uut.s_T[7:0]
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@28
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tb.uut.s_N_valid
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@22
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tb.uut.s_N[7:0]
26
@28
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tb.uut.s_data_stack_valid
28
@22
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tb.uut.s_Np_stack_ptr[4:0]
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tb.uut.s_Np_stack_ptr_next[4:0]
31
@1000200
32
-critical signals
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@c00200
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-PC
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@22
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tb.uut.s_PC[10:0]
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tb.uut.s_opcode[8:0]
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tb.uut.s_PC_plus1[10:0]
39
tb.uut.s_PC_jump[10:0]
40
tb.uut.s_PC_next[10:0]
41
@28
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tb.uut.s_bus_pc[1:0]
43
@1401200
44
-PC
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@c00200
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-R
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@22
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tb.uut.s_R[10:0]
49
tb.uut.s_R_pre[10:0]
50
@28
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tb.uut.s_bus_r
52
@1401200
53
-R
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@c00200
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-T
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@28
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tb.uut.s_T_valid
58
@22
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tb.uut.s_T[7:0]
60
tb.uut.s_T_pre[7:0]
61
@1401200
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-T
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@c00201
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-N
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@28
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tb.uut.s_N_valid
67
@22
68
tb.uut.s_N[7:0]
69
@28
70
tb.uut.s_bus_n[1:0]
71
@22
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tb.uut.s_Np_stack_ptr[4:0]
73
@1401201
74
-N
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@28
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tb.uut.s_interrupt_enabled
77
tb.uut.s_interrupt_enabled_change
78
tb.uut.s_interrupt_enabled_next
79
tb.uut.s_interrupt_holdoff
80
@22
81
tb.uut.s_math_rotate[7:0]
82
@28
83
tb.uut.s_outport
84
@22
85
tb.uut.s_return[1:0]
86
@28
87
tb.uut.s_stack[1:0]
88
[pattern_trace] 1
89
[pattern_trace] 0

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