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[/] [ssbcc/] [trunk/] [lib/] [9x8/] [tb/] [math/] [uc.9x8] - Blame information for rev 4

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# Copyright 2014, Sinclair R.F., Inc.
# Test bench for the math library.
 
ARCHITECTURE core/9x8 Verilog
 
INSTRUCTION     1024
DATA_STACK      128
RETURN_STACK    32
 
PORTCOMMENT     32-bit addition result
PERIPHERAL      big_outport     outport=O_VALUE         \
                                outsignal=o_value       \
                                width=96
OUTPORT         strobe          o_value_done            \
                                O_VALUE_DONE
 
PORTCOMMENT termination strobe
OUTPORT         strobe          o_terminate             \
                                O_TERMINATE
 
ASSEMBLY uc.s

Line No.	Rev	Author	Line
1	4	sinclairrf	`# Copyright 2014, Sinclair R.F., Inc.`
2			`# Test bench for the math library.`
3
4			`ARCHITECTURE core/9x8 Verilog`
5
6			`INSTRUCTION 1024`
7			`DATA_STACK 128`
8			`RETURN_STACK 32`
9
10			`PORTCOMMENT 32-bit addition result`
11			`PERIPHERAL big_outport outport=O_VALUE \`
12			`outsignal=o_value \`
13			`width=96`
14			`OUTPORT strobe o_value_done \`
15			`O_VALUE_DONE`
16
17			`PORTCOMMENT termination strobe`
18			`OUTPORT strobe o_terminate \`
19			`O_TERMINATE`
20
21			`ASSEMBLY uc.s`

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[/] [ssbcc/] [trunk/] [lib/] [9x8/] [tb/] [math/] [uc.9x8] - Blame information for rev 4