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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright 2008-2013 by Michael A. Morris, dba M. A. Morris & Associates
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//
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// All rights reserved. The source code contained herein is publicly released
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// under the terms and conditions of the GNU Lesser Public License. No part of
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// this source code may be reproduced or transmitted in any form or by any
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// means, electronic or mechanical, including photocopying, recording, or any
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// information storage and retrieval system in violation of the license under
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// which the source code is released.
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//
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// The source code contained herein is free; it may be redistributed and/or
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// modified in accordance with the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either version 2.1 of
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// the GNU Lesser General Public License, or any later version.
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//
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// The source code contained herein is freely released WITHOUT ANY WARRANTY;
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// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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// more details.)
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//
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// A copy of the GNU Lesser General Public License should have been received
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// along with the source code contained herein; if not, a copy can be obtained
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// by writing to:
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//
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// Free Software Foundation, Inc.
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// 51 Franklin Street, Fifth Floor
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// Boston, MA 02110-1301 USA
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//
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// Further, no use of this source code is permitted in any form or means
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// without inclusion of this banner prominently in any derived works.
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//
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// Michael A. Morris
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// Huntsville, AL
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//
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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///////////////////////////////////////////////////////////////////////////////
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// Company: M. A. Morris & Associates
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// Engineer: Michael A. Morris
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//
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// Create Date: 13:28:23 05/10/2008
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// Design Name: Synchronous Serial Peripheral (SSP) Interface UART
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// Module Name: ../VerilogCoponentsLib/SSP_UART/UART_BRG.v
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// Project Name: Verilog Components Library
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// Target Devices: XC3S50A-4VQG100I, XC3S20A-4VQG100I, XC3S700AN-4FFG484I
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// Tool versions: ISE 10.1i SP3
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//
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// Description: This module implements the Baud Rate Generator for the SSP
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// UART described for the 1700-0403 MicroBridge Option Card.
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//
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// The Baud Rate Generator implements the 16 baud rates defined
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// in Table 3 of the SSP UART Specification.
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//
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// Dependencies:
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//
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// Revision History:
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//
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// 0.01 08E10 MAM File Created
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//
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// 1.00 08E10 MAM Initial Release
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//
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// 1.10 08E13 MAM Changed interface so Prescaler and Divider values
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// passed directly in by removing Baud Rate ROM.
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//
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// 1.11 08E14 MAM Reduced width of divider from 10 to 8 bits.
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//
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// 1.20 08E15 MAM Changed the structure of the PSCntr and Divider
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// to use a multiplxer on the input to load or count
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// which results in a more efficient implementation.
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// Added a registered TC on the PSCntr which functions
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// to break the combinatorial logic chains and speed
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// counter implementations.
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//
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// 1.30 08G26 MAM Corrected initial condition of the PSCntr, which
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// caused the prescaler to always divide by two.
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// Removed FF in PSCntr TC path to remove the divide
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// by two issue. CE_16x output remains as registered.
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//
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// 2.00 11B06 MAM Converted to Verilog 2001.
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//
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// Additional Comments:
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//
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///////////////////////////////////////////////////////////////////////////////
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module UART_BRG(
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input Rst,
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input Clk,
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input [3:0] PS, // Baud Rate Generator Prescaler Load Value
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input [7:0] Div, // Baud Rate Generator Divider Load Value
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output reg CE_16x // Clock Enable Output - 16x Baud Rate Output
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);
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///////////////////////////////////////////////////////////////////////////////
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//
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// Local Signal Declarations
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//
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reg [ 3:0] PSCntr; // BRG Prescaler
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reg [ 7:0] Divider; // BRG Divider
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wire TC_PSCntr; // BRG Prescaler TC/Divider CE
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wire TC_Divider; // BRG Divider TC
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///////////////////////////////////////////////////////////////////////////////
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//
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// Implementation
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//
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// BRG Prescaler Counter
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always @(posedge Clk)
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begin
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if(Rst)
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PSCntr <= #1 0;
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else if(TC_PSCntr)
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PSCntr <= #1 PS;
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else
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PSCntr <= #1 PSCntr - 1;
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end
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assign TC_PSCntr = (PSCntr == 0);
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// BRG Divider
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always @(posedge Clk)
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begin
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if(Rst)
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Divider <= #1 0;
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else if(TC_Divider)
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Divider <= #1 Div;
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else if(TC_PSCntr)
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Divider <= #1 Divider - 1;
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end
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assign TC_Divider = TC_PSCntr & (Divider == 0);
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// Output 16x Bit Clock/CE
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always @(posedge Clk)
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begin
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if(Rst)
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CE_16x <= #1 1'b0;
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else
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CE_16x <= #1 TC_Divider;
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end
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endmodule
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