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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright 2008-2013 by Michael A. Morris, dba M. A. Morris & Associates
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//
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// All rights reserved. The source code contained herein is publicly released
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// under the terms and conditions of the GNU Lesser Public License. No part of
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// this source code may be reproduced or transmitted in any form or by any
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// means, electronic or mechanical, including photocopying, recording, or any
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// information storage and retrieval system in violation of the license under
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// which the source code is released.
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//
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// The source code contained herein is free; it may be redistributed and/or
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// modified in accordance with the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either version 2.1 of
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// the GNU Lesser General Public License, or any later version.
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//
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// The source code contained herein is freely released WITHOUT ANY WARRANTY;
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// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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// more details.)
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//
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// A copy of the GNU Lesser General Public License should have been received
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// along with the source code contained herein; if not, a copy can be obtained
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// by writing to:
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//
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// Free Software Foundation, Inc.
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// 51 Franklin Street, Fifth Floor
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// Boston, MA 02110-1301 USA
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//
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// Further, no use of this source code is permitted in any form or means
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// without inclusion of this banner prominently in any derived works.
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//
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// Michael A. Morris
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// Huntsville, AL
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//
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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///////////////////////////////////////////////////////////////////////////////
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// Company: M. A. Morris & Associates
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// Engineer: Michael A. Morris
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//
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// Create Date: 06:50:40 06/14/2008
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// Design Name: Synchronous Serial Peripheral (SSP) Interface UART
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// Module Name: ../VerilogCoponentsLib/SSP_UART/UART_RTO.v
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// Project Name: Verilog Components Library
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// Target Devices: XC3S50A-4VQG100I, XC3S20A-4VQG100I, XC3S700AN-4FFG484I
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// Tool versions: ISE 10.1i SP3
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//
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// Description: This module implements a receive timeout timer which sets a
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// flag to indicate that the timeout occured. The flag is cleared
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// by reset or by the reading of the Receive Holding Register.
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//
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// The Receive Timeout Val should be set by the client module to a
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// value which corresponds to the desired timeout value in terms
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// of the number of bit times. This module scales the 16x bit rate
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// clock enable by 16 to set the internal bit rate clock enable.
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// The client module provide the character frame length and the
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// number of characters to delay. The character frame length
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// varies as a function of the frame format, e.g. 8N1, 8E2, or
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// 7O1. The number of characters to delay for the timeout is a
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// fixed number of character periods, e.g. 3, in most cases. The
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// module allows these values to be independently specified.
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//
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//
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// Dependencies: none
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//
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// Revision History:
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//
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// 0.01 08E14 MAM File Created
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//
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// 1.00 08E14 MAM Initial Release
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//
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// 1.10 08E14 MAM Changed the input parameters to have two delay
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// parameters: CCntVal - character length; and
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// RTOVal - # characters to delay.
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// The result is a faster implementation, and one
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// the RTOVal can usually be set as a constant.
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//
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// 1.11 08E15 MAM Changed Module Name
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//
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// 2.00 11B06 MAM Converted to Verilog 2001.
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//
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// Additional Comments:
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//
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///////////////////////////////////////////////////////////////////////////////
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module UART_RTO(
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input Rst,
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input Clk,
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input CE_16x,
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input WE_RHR,
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input RE_RHR,
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input [3:0] CCntVal,
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input [3:0] RTOVal,
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output reg RcvTimeout
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);
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///////////////////////////////////////////////////////////////////////////////
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//
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// Local Signal Declarations
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//
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wire Clr_RTOArm;
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reg RTOArm;
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wire Clr_BCnt;
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reg [3:0] BCnt;
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reg TC_BCnt;
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wire Clr_CCnt;
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reg [3:0] CCnt;
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reg TC_CCnt;
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wire Clr_RTOCnt, CE_RTOCnt;
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reg [3:0] RTOCnt;
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reg TC_RTOCnt;
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wire Clr_RTO, CE_RTO;
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///////////////////////////////////////////////////////////////////////////////
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//
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// Implementation
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//
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// RTO Arm FF
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// Armed with each received character, cleared by Rst, RE_RHR, or timeout
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//
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assign Clr_RTOArm = RE_RHR | CE_RTO;
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always @(posedge Clk)
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begin
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if(Rst)
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RTOArm <= #1 0;
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else if(Clr_RTOArm)
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RTOArm <= #1 0;
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else if(WE_RHR)
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RTOArm <= #1 1;
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end
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///////////////////////////////////////////////////////////////////////////////
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//
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// Bit Rate Divider
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// Held in reset until RTO Armed or if Rst asserted
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//
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assign Clr_BCnt = Rst | WE_RHR | Clr_RTOArm | ~RTOArm;
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always @(posedge Clk)
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begin
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if(Clr_BCnt)
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BCnt <= #1 0;
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else if(CE_16x)
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BCnt <= #1 BCnt + 1;
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end
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always @(posedge Clk)
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begin
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if(Clr_BCnt)
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TC_BCnt <= #1 0;
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else if(CE_16x)
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TC_BCnt <= #1 (BCnt == 4'b1110);
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end
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///////////////////////////////////////////////////////////////////////////////
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//
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// Character Frame Divider
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// Held in reset until RTO Armed or if Rst asserted
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//
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assign Clr_CCnt = Clr_BCnt;
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assign CE_CCnt = CE_16x & TC_BCnt;
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always @(posedge Clk)
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begin
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if(Clr_CCnt)
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CCnt <= #1 CCntVal;
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else if(CE_CCnt)
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CCnt <= #1 ((TC_CCnt) ? CCntVal : CCnt - 1);
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end
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always @(posedge Clk)
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begin
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if(Clr_CCnt)
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TC_CCnt <= #1 0;
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else if(CE_16x)
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TC_CCnt <= #1 (CCnt == 0);
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end
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///////////////////////////////////////////////////////////////////////////////
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//
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// Receive Timeout Counter
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// Held in reset until RTO Armed or if Rst asserted
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// Counts bit periods when RTO Armed
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assign Clr_RTOCnt = Clr_BCnt;
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assign CE_RTOCnt = CE_16x & TC_BCnt & TC_CCnt;
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always @(posedge Clk)
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begin
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if(Clr_RTOCnt)
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RTOCnt <= #1 RTOVal;
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else if(CE_RTOCnt)
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RTOCnt <= #1 ((TC_RTOCnt) ? RTOVal : RTOCnt - 1);
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end
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always @(posedge Clk)
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begin
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if(Clr_RTOCnt)
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TC_RTOCnt <= #1 0;
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else if(CE_16x)
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TC_RTOCnt <= #1 (RTOCnt == 0);
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end
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///////////////////////////////////////////////////////////////////////////////
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//
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// Receive Timeout Latch
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// Cleared by Rst or any read of the RHR
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// Set by RTOCnt terminal count
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assign Clr_RTO = RE_RHR;
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assign CE_RTO = CE_16x & TC_BCnt & TC_CCnt & TC_RTOCnt;
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always @(posedge Clk)
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begin
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if(Rst)
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RcvTimeout <= #1 0;
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else if(Clr_RTO)
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RcvTimeout <= #1 0;
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else if(CE_RTO)
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RcvTimeout <= #1 1;
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end
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endmodule
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