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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright 2008-2013 by Michael A. Morris, dba M. A. Morris & Associates
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//
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// All rights reserved. The source code contained herein is publicly released
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// under the terms and conditions of the GNU Lesser Public License. No part of
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// this source code may be reproduced or transmitted in any form or by any
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// means, electronic or mechanical, including photocopying, recording, or any
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// information storage and retrieval system in violation of the license under
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// which the source code is released.
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//
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// The source code contained herein is free; it may be redistributed and/or
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// modified in accordance with the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either version 2.1 of
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// the GNU Lesser General Public License, or any later version.
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//
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// The source code contained herein is freely released WITHOUT ANY WARRANTY;
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// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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// more details.)
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//
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// A copy of the GNU Lesser General Public License should have been received
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// along with the source code contained herein; if not, a copy can be obtained
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// by writing to:
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//
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// Free Software Foundation, Inc.
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// 51 Franklin Street, Fifth Floor
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// Boston, MA 02110-1301 USA
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//
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// Further, no use of this source code is permitted in any form or means
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// without inclusion of this banner prominently in any derived works.
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//
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// Michael A. Morris
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// Huntsville, AL
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//
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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///////////////////////////////////////////////////////////////////////////////
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// Company: M. A. Morris & Associates
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// Engineer: Michael A. Morris
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//
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// Create Date: 19:16:35 05/10/2008
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// Design Name: Synchronous Serial Peripheral (SSP) Interface UART
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// Module Name: ../VerilogCoponentsLib/SSP_UART/tb_UART_BRG.v
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// Project Name: Verilog Components Library
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// Target Devices: XC3S50A-4VQG100I, XC3S20A-4VQG100I, XC3S700AN-4FFG484I
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// Tool versions: ISE 10.1i SP3
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//
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// Description: This test bench is intended to test the BRG module for the SSP
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// UART.
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//
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// Verilog Test Fixture created by ISE for module: UART_BRG
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//
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// Dependencies:
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//
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// Revision History:
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//
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// 0.01 08E10 MAM File Created
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//
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module tb_UART_BRG_v;
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// Inputs
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reg Rst;
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reg Clk;
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reg [3:0] PS;
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reg [7:0] Div;
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reg [3:0] Baud;
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// Outputs
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wire CE_16x;
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// Instantiate the Unit Under Test (UUT)
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UART_BRG uut (
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.Rst(Rst),
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.Clk(Clk),
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.PS(PS),
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.Div(Div),
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.CE_16x(CE_16x)
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);
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initial begin
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// Initialize Inputs
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Rst = 1;
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Clk = 0;
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Baud = 0;
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// Wait 100 ns for global reset to finish
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#101;
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Rst = 0;
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// Add stimulus here
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@(posedge Clk);
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@(posedge Clk);
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@(posedge Clk);
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@(posedge Clk);
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@(posedge Clk);
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@(posedge Clk);
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@(posedge Clk);
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@(posedge Clk);
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@(posedge Clk) #1 Baud = 1;
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@(negedge CE_16x) #1 Baud = 2;
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@(negedge CE_16x) #1 Baud = 3;
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@(negedge CE_16x);
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@(negedge CE_16x) #1 Baud = 4;
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@(negedge CE_16x) #1 Baud = 5;
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@(negedge CE_16x) #1 Baud = 6;
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@(negedge CE_16x) #1 Baud = 7;
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@(negedge CE_16x) #1 Baud = 8;
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@(negedge CE_16x) #1 Baud = 9;
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@(negedge CE_16x) #1 Baud = 10;
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@(negedge CE_16x) #1 Baud = 11;
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@(negedge CE_16x) #1 Baud = 12;
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@(negedge CE_16x) #1 Baud = 13;
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@(negedge CE_16x) #1 Baud = 14;
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@(negedge CE_16x) #1 Baud = 15;
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@(negedge CE_16x)
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@(negedge CE_16x) Baud = 0;
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end
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///////////////////////////////////////////////////////////////////////////////
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//
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// Clocks
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//
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always #10.416 Clk = ~Clk;
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///////////////////////////////////////////////////////////////////////////////
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//
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// Simulation Drivers/Models
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//
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// Baud Rate Generator's PS and Div for defined Baud Rates (48 MHz Oscillator)
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always @(Baud)
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begin
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case(Baud)
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4'b0000 : {Div, PS} <= 12'b0000_0000_0000; // Div = 1; PS = 1
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4'b0001 : {Div, PS} <= 12'b0000_0001_0000; // Div = 2; PS = 1
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4'b0010 : {Div, PS} <= 12'b0000_0101_0000; // Div = 6; PS = 1
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4'b0011 : {Div, PS} <= 12'b0000_1111_0000; // Div = 16; PS = 1
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4'b0100 : {Div, PS} <= 12'b0000_0000_1100; // Div = 1; PS = 13
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4'b0101 : {Div, PS} <= 12'b0000_0001_1100; // Div = 2; PS = 13
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4'b0110 : {Div, PS} <= 12'b0000_0010_1100; // Div = 3; PS = 13
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4'b0111 : {Div, PS} <= 12'b0000_0011_1100; // Div = 4; PS = 13
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4'b1000 : {Div, PS} <= 12'b0000_0101_1100; // Div = 6; PS = 13
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4'b1001 : {Div, PS} <= 12'b0000_1011_1100; // Div = 12; PS = 13
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4'b1010 : {Div, PS} <= 12'b0001_0111_1100; // Div = 24; PS = 13
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4'b1011 : {Div, PS} <= 12'b0010_1111_1100; // Div = 48; PS = 13
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4'b1100 : {Div, PS} <= 12'b0101_1111_1100; // Div = 96; PS = 13
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4'b1101 : {Div, PS} <= 12'b1011_1111_1100; // Div = 192; PS = 13
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4'b1110 : {Div, PS} <= 12'b0111_1111_1100; // Div = 128; PS = 13
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4'b1111 : {Div, PS} <= 12'b1111_1111_1100; // Div = 256; PS = 13
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endcase
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end
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endmodule
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