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[/] [ssram/] [trunk/] [ssram.vhd] - Blame information for rev 4

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--
--
--      S S R A M  i n t e r f a c e
--
-- various components for ssrams
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
package SSRAM is
        component ssram_conn is
        generic(
                DWIDTH  : positive := 16;
                AWIDTH : positive := 18
        );
        port (
                clk : in std_logic;
                A : in unsigned(AWIDTH -1 downto 0);
                Din : in std_logic_vector(DWIDTH -1 downto 0);
                Dout : out std_logic_vector(DWIDTH -1 downto 0);
                rw : in std_logic;
                bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');
 
                ssramA : out unsigned(AWIDTH -1 downto 0);
                ssramD : inout std_logic_vector(DWIDTH -1 downto 0);
                ssramRW : out std_logic;
                ssramBW : out std_logic_vector((DWIDTH/8) downto 0)
        );
        end component ssram_conn;
 
        component cs_ssram is
        generic(
                DWIDTH : positive := 16;
                AWIDTH : positive := 18
        );
        port (
                clk : in std_logic;
                clk_div2 : in std_logic;                -- clk divided by 2
 
                p0_A : in unsigned(AWIDTH -1 downto 0);
                p0_Din : in std_logic_vector(DWIDTH -1 downto 0);
                p0_Dout : out std_logic_vector(DWIDTH -1 downto 0);
                p0_rw : in std_logic;
                p0_bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');
 
                p1_A : in unsigned(AWIDTH -1 downto 0);
                p1_Din : in std_logic_vector(DWIDTH -1 downto 0);
                p1_Dout : out std_logic_vector(DWIDTH -1 downto 0);
                p1_rw : in std_logic;
                p1_bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');
 
                ssramA : out unsigned(AWIDTH -1 downto 0);
                ssramD : inout std_logic_vector(DWIDTH -1 downto 0);
                ssramRW : out std_logic;
                ssramBW : out std_logic_vector((DWIDTH/8) downto 0)
        );
        end component cs_ssram;
 
end package SSRAM;
 
--
--
-- SSRAM cycle shared memory implementation
--
-- ssram can be accessed by 2 ports at clk_div2 frequency. SSRAM operates at clk frequency
-- clk_div2 is actually a clk_en signal (no extra clock-domain)
--
-- read command: data valid after 3 clk_div2 cycles
-- 1) set address, RW = '1' (read command)
-- 2) present address/RW to ssram
-- 3) ssram presents data
-- 4) data (p0_dout/p1_dout) valid
-- 5) take/use data
--
-- note: p0_dout Tsu = 1 clk_div2 cycle
--       p1_dout Tsu = 1 clk cycle (so half of p0_dout Tsu)
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity cs_ssram is
        generic(
                DWIDTH : positive := 16;
                AWIDTH : positive := 18
        );
        port (
                clk : in std_logic;
                clk_div2 : in std_logic;                -- clk divided by 2
 
                p0_A : in unsigned(AWIDTH -1 downto 0);
                p0_Din : in std_logic_vector(DWIDTH -1 downto 0);
                p0_Dout : out std_logic_vector(DWIDTH -1 downto 0);
                p0_rw : in std_logic;
                p0_bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');
 
                p1_A : in unsigned(AWIDTH -1 downto 0);
                p1_Din : in std_logic_vector(DWIDTH -1 downto 0);
                p1_Dout : out std_logic_vector(DWIDTH -1 downto 0);
                p1_rw : in std_logic;
                p1_bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');
 
                ssramA : out unsigned(AWIDTH -1 downto 0);
                ssramD : inout std_logic_vector(DWIDTH -1 downto 0);
                ssramRW : out std_logic;
                ssramBW : out std_logic_vector((DWIDTH/8) downto 0)
        );
end entity cs_ssram;
 
architecture structural of cs_ssram is
        component ssram_conn is
        generic(
                DWIDTH  : positive;
                AWIDTH : positive
        );
        port (
                clk : in std_logic;
                A : in unsigned(AWIDTH -1 downto 0);
                Din : in std_logic_vector(DWIDTH -1 downto 0);
                Dout : out std_logic_vector(DWIDTH -1 downto 0);
                rw : in std_logic;
                bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');
 
                ssramA : out unsigned(AWIDTH -1 downto 0);
                ssramD : inout std_logic_vector(DWIDTH -1 downto 0);
                ssramRW : out std_logic;
                ssramBW : out std_logic_vector((DWIDTH/8) downto 0)
        );
        end component ssram_conn;
 
        signal A : unsigned(AWIDTH -1 downto 0);
        signal Din : std_logic_vector(DWIDTH -1 downto 0);       -- from SSRAMs
        signal Dout : std_logic_vector(DWIDTH -1 downto 0);      -- towards SSRAMs
        signal BW : std_logic_vector((DWIDTH/8) downto 0);
        signal RW : std_logic;
begin
 
        -- mux address / data-in / rw / bw
        gen_muxs: process (clk)
                variable iA : unsigned(AWIDTH -1 downto 0);
                variable iDout : std_logic_vector(DWIDTH -1 downto 0);
                variable iRW : std_logic;
                variable iBW : std_logic_vector((DWIDTH/8) downto 0);
        begin
                if (clk_div2 = '0') then
                        iA := p0_A;
                        iDout := p0_Din;
                        iRW := p0_rw;
                        for n in 0 to (DWIDTH/8) loop
                                iBW(n) := p0_bw(n);
                        end loop;
                else -- clk_div2 = '1'
                        iA := p1_A;
                        iDout := p1_Din;
                        iRW := p1_rw;
                        for n in 0 to (DWIDTH/8) loop
                                iBW(n) := p1_bw(n);
                        end loop;
                end if;
 
                if (clk'event and clk = '1') then
                        A <= iA;
                        Dout <= iDout;
                        RW <= iRW;
                        BW <= iBW;
                end if;
        end process gen_muxs;
 
        -- instert ssram IO controller
        ssram_io_ctrl: ssram_conn generic map (DWIDTH => DWIDTH, AWIDTH => AWIDTH)
                        port map (clk, A, Dout, Din, RW, bw, ssramA, ssramD, ssramRW, ssramBW);
 
        -- demux data from ssram
        demux_din: process(clk)
        begin
                if (clk'event and clk = '1') then
                        if (clk_div2 = '1') then        -- switched
                                p0_Dout <= Din;
                        else
                                p1_Dout <= Din;
                        end if;
                end if;
        end process demux_din;
 
end architecture structural; -- of cs_ssram
 
--
--
--      SSRAM physical connection (IO) controller
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity ssram_conn is
        generic(
                DWIDTH  : positive := 16;
                AWIDTH : positive := 18
        );
        port (
                clk : in std_logic;
                A : in unsigned(AWIDTH -1 downto 0);
                Din : in std_logic_vector(DWIDTH -1 downto 0);
                Dout : out std_logic_vector(DWIDTH -1 downto 0);
                rw : in std_logic;
                bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');
 
                ssramA : out unsigned(AWIDTH -1 downto 0);
                ssramD : inout std_logic_vector(DWIDTH -1 downto 0);
                ssramRW : out std_logic;
                ssramBW : out std_logic_vector((DWIDTH/8) downto 0)
        );
end entity ssram_conn;
 
architecture structural of ssram_conn is
        signal dD, ddD, dddD : std_logic_vector(DWIDTH -1 downto 0);
        signal dsel, ddsel : std_logic;
        signal dddSel : std_logic_vector(DWIDTH -1 downto 0);
        attribute preserve_signal : boolean;
        attribute preserve_signal of dddSel: signal is true;    -- instruct compiler to leave these signals
        attribute preserve_signal of dddD: signal is true;
begin
        process(clk, dddD, dddSel)
        begin
                if(clk'event and clk = '1') then
                        -- compensate ssram pipeline delay
                        dD <= Din;                                              -- present address / rw
                        ddD <= dD;                                              -- ssram takes address / rw over
                        dddD <= ddD;                                    -- present data
                        dsel <= not RW;
                        ddsel <= dsel;
 
                        for n in 0 to (DWIDTH -1) loop
                                dddsel(n) <= ddsel;
                        end loop;
 
                        Dout <= ssramD;
                        ssramA <= A;
                        ssramRW <= RW;
                        ssramBW <= BW;
                end if;
 
                for n in 0 to (DWIDTH -1) loop
                        if (dddSel(n) = '1') then
                                ssramD(n) <= dddD(n);
                        else
                                ssramD(n) <= 'Z';
                        end if;
                end loop;
 
        end process;
end architecture structural; -- of ssram_conn

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[/] [ssram/] [trunk/] [ssram.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	rherveille	`--`
2			`--`
3			`-- S S R A M i n t e r f a c e`
4			`--`
5			`-- various components for ssrams`
6			`--`
7
8			`library ieee;`
9			`use ieee.std_logic_1164.all;`
10			`use ieee.std_logic_arith.all;`
11
12			`package SSRAM is`
13			`component ssram_conn is`
14			`generic(`
15			`DWIDTH : positive := 16;`
16			`AWIDTH : positive := 18`
17			`);`
18			`port (`
19			`clk : in std_logic;`
20			`A : in unsigned(AWIDTH -1 downto 0);`
21			`Din : in std_logic_vector(DWIDTH -1 downto 0);`
22			`Dout : out std_logic_vector(DWIDTH -1 downto 0);`
23			`rw : in std_logic;`
24			`bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');`
25
26			`ssramA : out unsigned(AWIDTH -1 downto 0);`
27			`ssramD : inout std_logic_vector(DWIDTH -1 downto 0);`
28			`ssramRW : out std_logic;`
29			`ssramBW : out std_logic_vector((DWIDTH/8) downto 0)`
30			`);`
31			`end component ssram_conn;`
32
33			`component cs_ssram is`
34			`generic(`
35			`DWIDTH : positive := 16;`
36			`AWIDTH : positive := 18`
37			`);`
38			`port (`
39			`clk : in std_logic;`
40			`clk_div2 : in std_logic; -- clk divided by 2`
41
42			`p0_A : in unsigned(AWIDTH -1 downto 0);`
43			`p0_Din : in std_logic_vector(DWIDTH -1 downto 0);`
44			`p0_Dout : out std_logic_vector(DWIDTH -1 downto 0);`
45			`p0_rw : in std_logic;`
46			`p0_bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');`
47
48			`p1_A : in unsigned(AWIDTH -1 downto 0);`
49			`p1_Din : in std_logic_vector(DWIDTH -1 downto 0);`
50			`p1_Dout : out std_logic_vector(DWIDTH -1 downto 0);`
51			`p1_rw : in std_logic;`
52			`p1_bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');`
53
54			`ssramA : out unsigned(AWIDTH -1 downto 0);`
55			`ssramD : inout std_logic_vector(DWIDTH -1 downto 0);`
56			`ssramRW : out std_logic;`
57			`ssramBW : out std_logic_vector((DWIDTH/8) downto 0)`
58			`);`
59			`end component cs_ssram;`
60
61			`end package SSRAM;`
62
63			`--`
64			`--`
65			`-- SSRAM cycle shared memory implementation`
66			`--`
67			`-- ssram can be accessed by 2 ports at clk_div2 frequency. SSRAM operates at clk frequency`
68			`-- clk_div2 is actually a clk_en signal (no extra clock-domain)`
69			`--`
70			`-- read command: data valid after 3 clk_div2 cycles`
71			`-- 1) set address, RW = '1' (read command)`
72			`-- 2) present address/RW to ssram`
73			`-- 3) ssram presents data`
74			`-- 4) data (p0_dout/p1_dout) valid`
75			`-- 5) take/use data`
76			`--`
77			`-- note: p0_dout Tsu = 1 clk_div2 cycle`
78			`-- p1_dout Tsu = 1 clk cycle (so half of p0_dout Tsu)`
79
80			`library ieee;`
81			`use ieee.std_logic_1164.all;`
82			`use ieee.std_logic_arith.all;`
83
84			`entity cs_ssram is`
85			`generic(`
86			`DWIDTH : positive := 16;`
87			`AWIDTH : positive := 18`
88			`);`
89			`port (`
90			`clk : in std_logic;`
91			`clk_div2 : in std_logic; -- clk divided by 2`
92
93			`p0_A : in unsigned(AWIDTH -1 downto 0);`
94			`p0_Din : in std_logic_vector(DWIDTH -1 downto 0);`
95			`p0_Dout : out std_logic_vector(DWIDTH -1 downto 0);`
96			`p0_rw : in std_logic;`
97			`p0_bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');`
98
99			`p1_A : in unsigned(AWIDTH -1 downto 0);`
100			`p1_Din : in std_logic_vector(DWIDTH -1 downto 0);`
101			`p1_Dout : out std_logic_vector(DWIDTH -1 downto 0);`
102			`p1_rw : in std_logic;`
103			`p1_bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');`
104
105			`ssramA : out unsigned(AWIDTH -1 downto 0);`
106			`ssramD : inout std_logic_vector(DWIDTH -1 downto 0);`
107			`ssramRW : out std_logic;`
108			`ssramBW : out std_logic_vector((DWIDTH/8) downto 0)`
109			`);`
110			`end entity cs_ssram;`
111
112			`architecture structural of cs_ssram is`
113			`component ssram_conn is`
114			`generic(`
115			`DWIDTH : positive;`
116			`AWIDTH : positive`
117			`);`
118			`port (`
119			`clk : in std_logic;`
120			`A : in unsigned(AWIDTH -1 downto 0);`
121			`Din : in std_logic_vector(DWIDTH -1 downto 0);`
122			`Dout : out std_logic_vector(DWIDTH -1 downto 0);`
123			`rw : in std_logic;`
124			`bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');`
125
126			`ssramA : out unsigned(AWIDTH -1 downto 0);`
127			`ssramD : inout std_logic_vector(DWIDTH -1 downto 0);`
128			`ssramRW : out std_logic;`
129			`ssramBW : out std_logic_vector((DWIDTH/8) downto 0)`
130			`);`
131			`end component ssram_conn;`
132
133			`signal A : unsigned(AWIDTH -1 downto 0);`
134			`signal Din : std_logic_vector(DWIDTH -1 downto 0); -- from SSRAMs`
135			`signal Dout : std_logic_vector(DWIDTH -1 downto 0); -- towards SSRAMs`
136			`signal BW : std_logic_vector((DWIDTH/8) downto 0);`
137			`signal RW : std_logic;`
138			`begin`
139
140			`-- mux address / data-in / rw / bw`
141			`gen_muxs: process (clk)`
142			`variable iA : unsigned(AWIDTH -1 downto 0);`
143			`variable iDout : std_logic_vector(DWIDTH -1 downto 0);`
144			`variable iRW : std_logic;`
145			`variable iBW : std_logic_vector((DWIDTH/8) downto 0);`
146			`begin`
147			`if (clk_div2 = '0') then`
148			`iA := p0_A;`
149			`iDout := p0_Din;`
150			`iRW := p0_rw;`
151			`for n in 0 to (DWIDTH/8) loop`
152			`iBW(n) := p0_bw(n);`
153			`end loop;`
154			`else -- clk_div2 = '1'`
155			`iA := p1_A;`
156			`iDout := p1_Din;`
157			`iRW := p1_rw;`
158			`for n in 0 to (DWIDTH/8) loop`
159			`iBW(n) := p1_bw(n);`
160			`end loop;`
161			`end if;`
162
163			`if (clk'event and clk = '1') then`
164			`A <= iA;`
165			`Dout <= iDout;`
166			`RW <= iRW;`
167			`BW <= iBW;`
168			`end if;`
169			`end process gen_muxs;`
170
171			`-- instert ssram IO controller`
172			`ssram_io_ctrl: ssram_conn generic map (DWIDTH => DWIDTH, AWIDTH => AWIDTH)`
173			`port map (clk, A, Dout, Din, RW, bw, ssramA, ssramD, ssramRW, ssramBW);`
174
175			`-- demux data from ssram`
176			`demux_din: process(clk)`
177			`begin`
178			`if (clk'event and clk = '1') then`
179			`if (clk_div2 = '1') then -- switched`
180			`p0_Dout <= Din;`
181			`else`
182			`p1_Dout <= Din;`
183			`end if;`
184			`end if;`
185			`end process demux_din;`
186
187			`end architecture structural; -- of cs_ssram`
188
189			`--`
190			`--`
191			`-- SSRAM physical connection (IO) controller`
192			`--`
193			`--`
194			`library ieee;`
195			`use ieee.std_logic_1164.all;`
196			`use ieee.std_logic_arith.all;`
197
198			`entity ssram_conn is`
199			`generic(`
200			`DWIDTH : positive := 16;`
201			`AWIDTH : positive := 18`
202			`);`
203			`port (`
204			`clk : in std_logic;`
205			`A : in unsigned(AWIDTH -1 downto 0);`
206			`Din : in std_logic_vector(DWIDTH -1 downto 0);`
207			`Dout : out std_logic_vector(DWIDTH -1 downto 0);`
208			`rw : in std_logic;`
209			`bw : in std_logic_vector((DWIDTH/8) downto 0) := (others => '0');`
210
211			`ssramA : out unsigned(AWIDTH -1 downto 0);`
212			`ssramD : inout std_logic_vector(DWIDTH -1 downto 0);`
213			`ssramRW : out std_logic;`
214			`ssramBW : out std_logic_vector((DWIDTH/8) downto 0)`
215			`);`
216			`end entity ssram_conn;`
217
218			`architecture structural of ssram_conn is`
219			`signal dD, ddD, dddD : std_logic_vector(DWIDTH -1 downto 0);`
220			`signal dsel, ddsel : std_logic;`
221			`signal dddSel : std_logic_vector(DWIDTH -1 downto 0);`
222			`attribute preserve_signal : boolean;`
223			`attribute preserve_signal of dddSel: signal is true; -- instruct compiler to leave these signals`
224			`attribute preserve_signal of dddD: signal is true;`
225			`begin`
226			`process(clk, dddD, dddSel)`
227			`begin`
228			`if(clk'event and clk = '1') then`
229			`-- compensate ssram pipeline delay`
230			`dD <= Din; -- present address / rw`
231			`ddD <= dD; -- ssram takes address / rw over`
232			`dddD <= ddD; -- present data`
233			`dsel <= not RW;`
234			`ddsel <= dsel;`
235
236			`for n in 0 to (DWIDTH -1) loop`
237			`dddsel(n) <= ddsel;`
238			`end loop;`
239
240			`Dout <= ssramD;`
241			`ssramA <= A;`
242			`ssramRW <= RW;`
243			`ssramBW <= BW;`
244			`end if;`
245
246			`for n in 0 to (DWIDTH -1) loop`
247			`if (dddSel(n) = '1') then`
248			`ssramD(n) <= dddD(n);`
249			`else`
250			`ssramD(n) <= 'Z';`
251			`end if;`
252			`end loop;`
253
254			`end process;`
255			`end architecture structural; -- of ssram_conn`