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[/] [statled/] [trunk/] [rtl/] [statled.v] - Blame information for rev 4

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1 2 mitko
`timescale 1ns / 100ps
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/******************************************************************************
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*  Status LED module
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*
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*  Use single LED ouput to displays various internal states as blink codes.
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*  http://www.opencores.org/cores/statled
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*
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******************************************************************************/
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module statled (
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    input           clk,
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    input           rst,
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    input  [3:0]    status,
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    output          led
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);
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`include "statled_par.v"
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reg [32:0]       pre;            // Prescaler
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reg [7:0]        bcnt;           // Bit counter
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reg [15:0]       lsr;            // LED shift register 
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reg [15:0]       cr;             // Code register
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reg [3:0]        str;            // Status register
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wire            rate;           // LED rate
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//-----------------------------------------------------------------------------
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// LED rate  
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//
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always @(posedge clk or posedge rst)
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        if (rst)
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        pre <= #tDLY 0;
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    else if (rate)
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        pre <= #tDLY 0;
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    else
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        pre <= #tDLY pre + 1;
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assign rate = (pre == STATLED_PULSE_CLKCNT);
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//-----------------------------------------------------------------------------
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// Capture status inputs
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//
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always @(posedge clk or posedge rst)
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        if (rst)
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        str <= #tDLY 0;
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    else
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        str <= #tDLY status;
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//-----------------------------------------------------------------------------
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// Shift register and bit counter
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//
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always @(posedge clk or posedge rst)
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        if (rst)
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        bcnt <= #tDLY 15;
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        else if (bcnt == 16)
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        bcnt <= #tDLY 0;
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        else if (rate)
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        bcnt <= #tDLY bcnt + 1;
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always @(posedge clk or posedge rst)
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        if (rst)
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        lsr <= #tDLY 0;
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        else if (bcnt == 16)
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        lsr <= #tDLY cr;
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        else if (rate)
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        lsr <= #tDLY lsr << 1;
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assign led = rst? 1 : lsr[15];
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//-----------------------------------------------------------------------------
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// Codes 
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//
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always @*
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    case(str)
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        0: cr = CODE_50_50;           // Default code
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        1: cr = CODE_ONE;             // State 1 
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        2: cr = CODE_TWO;             // State 2
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        3: cr = CODE_THREE;           // ....
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        4: cr = CODE_FOUR;            //
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        5: cr = CODE_FIVE;            //
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        6: cr = CODE_SIX;             //
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        default: cr = 0;
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    endcase
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endmodule

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