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[/] [structural_vhdl/] [tags/] [vlsi/] [inout_port/] [control_dataout.vst] - Blame information for rev 2

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-- VHDL structural description generated from `control_dataout`
--              date : Mon Aug 27 06:38:12 2001
 
 
-- Entity Declaration
 
ENTITY control_dataout IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  cp_ready : in BIT;    -- cp_ready
  emp_bufout : in BIT;  -- emp_bufout
  en_bufout : inout BIT;        -- en_bufout
  req_cp : out BIT;     -- req_cp
  cp_sended : out BIT;  -- cp_sended
  n_block : inout BIT;  -- n_block
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END control_dataout;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF control_dataout IS
  COMPONENT on12_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT o3_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT na2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT na3_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT nao22_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT an12_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT o2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT no3_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT xr2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT inv_x1
    port (
    i : in BIT; -- i
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT a3_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT sff1_x4
    port (
    ck : in BIT;        -- ck
    i : in BIT; -- i
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL auxsc11 : BIT; -- auxsc11
  SIGNAL auxsc12 : BIT; -- auxsc12
  SIGNAL auxsc15 : BIT; -- auxsc15
  SIGNAL auxsc21 : BIT; -- auxsc21
  SIGNAL auxsc19 : BIT; -- auxsc19
  SIGNAL auxsc16 : BIT; -- auxsc16
  SIGNAL auxsc20 : BIT; -- auxsc20
  SIGNAL auxsc32 : BIT; -- auxsc32
  SIGNAL auxsc8 : BIT;  -- auxsc8
  SIGNAL auxsc33 : BIT; -- auxsc33
  SIGNAL auxsc34 : BIT; -- auxsc34
  SIGNAL auxsc35 : BIT; -- auxsc35
  SIGNAL auxsc36 : BIT; -- auxsc36
  SIGNAL auxsc43 : BIT; -- auxsc43
  SIGNAL auxsc44 : BIT; -- auxsc44
  SIGNAL auxsc45 : BIT; -- auxsc45
  SIGNAL auxsc46 : BIT; -- auxsc46
  SIGNAL auxsc47 : BIT; -- auxsc47
  SIGNAL auxsc48 : BIT; -- auxsc48
  SIGNAL auxsc9 : BIT;  -- auxsc9
  SIGNAL auxsc10 : BIT; -- auxsc10
  SIGNAL auxsc6 : BIT;  -- auxsc6
  SIGNAL auxreg3 : BIT; -- auxreg3
  SIGNAL auxreg2 : BIT; -- auxreg2
  SIGNAL auxreg1 : BIT; -- auxreg1
 
BEGIN
 
  cp_sended : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => cp_sended,
    i2 => auxsc36,
    i1 => auxsc33,
    i0 => rst);
  req_cp : on12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => req_cp,
    i1 => auxsc48,
    i0 => auxsc11);
  auxsc6 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc6,
    i2 => auxsc10,
    i1 => auxsc9,
    i0 => rst);
  auxsc10 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc10,
    i2 => rst,
    i1 => emp_bufout,
    i0 => auxsc8);
  auxsc9 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc9,
    i1 => auxreg3,
    i0 => auxreg2);
  auxsc48 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc48,
    i2 => auxsc47,
    i1 => auxreg3,
    i0 => auxsc44);
  auxsc47 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc47,
    i => auxsc46);
  auxsc46 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc46,
    i1 => auxreg1,
    i0 => auxsc45);
  auxsc45 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc45,
    i => emp_bufout);
  auxsc44 : na3_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc44,
    i2 => auxsc43,
    i1 => auxsc8,
    i0 => auxsc21);
  auxsc43 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc43,
    i => auxreg2);
  auxsc36 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc36,
    i => auxsc35);
  auxsc35 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc35,
    i1 => auxsc34,
    i0 => rst);
  auxsc34 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc34,
    i1 => auxreg1,
    i0 => emp_bufout);
  auxsc33 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc33,
    i2 => auxsc8,
    i1 => auxreg3,
    i0 => auxsc32);
  auxsc8 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc8,
    i => auxreg1);
  auxsc32 : an12_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc32,
    i1 => auxreg2,
    i0 => emp_bufout);
  auxsc20 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc20,
    i1 => auxsc16,
    i0 => auxsc19);
  auxsc16 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc16,
    i1 => auxreg2,
    i0 => emp_bufout);
  auxsc19 : no3_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc19,
    i2 => auxreg2,
    i1 => auxreg1,
    i0 => auxsc21);
  auxsc21 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc21,
    i => cp_ready);
  auxsc15 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc15,
    i => auxreg3);
  auxsc12 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc12,
    i1 => auxreg3,
    i0 => auxreg2);
  auxsc11 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc11,
    i => rst);
  auxinit1_a : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => n_block,
    i1 => auxsc12,
    i0 => auxsc11);
  auxinit2_a : a3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => en_bufout,
    i2 => auxsc20,
    i1 => auxsc11,
    i0 => auxsc15);
  current_state_0 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg1,
    i => auxsc6,
    ck => clk);
  current_state_1 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg2,
    i => n_block,
    ck => clk);
  current_state_2 : sff1_x4
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxreg3,
    i => en_bufout,
    ck => clk);
 
end VST;

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Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [tags/] [vlsi/] [inout_port/] [control_dataout.vst] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `control_dataout`
2			`-- date : Mon Aug 27 06:38:12 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY control_dataout IS`
8			`PORT (`
9			`clk : in BIT; -- clk`
10			`rst : in BIT; -- rst`
11			`cp_ready : in BIT; -- cp_ready`
12			`emp_bufout : in BIT; -- emp_bufout`
13			`en_bufout : inout BIT; -- en_bufout`
14			`req_cp : out BIT; -- req_cp`
15			`cp_sended : out BIT; -- cp_sended`
16			`n_block : inout BIT; -- n_block`
17			`vdd : in BIT; -- vdd`
18			`vss : in BIT -- vss`
19			`);`
20			`END control_dataout;`
21
22			`-- Architecture Declaration`
23
24			`ARCHITECTURE VST OF control_dataout IS`
25			`COMPONENT on12_x1`
26			`port (`
27			`i0 : in BIT; -- i0`
28			`i1 : in BIT; -- i1`
29			`q : out BIT; -- q`
30			`vdd : in BIT; -- vdd`
31			`vss : in BIT -- vss`
32			`);`
33			`END COMPONENT;`
34
35			`COMPONENT o3_x2`
36			`port (`
37			`i0 : in BIT; -- i0`
38			`i1 : in BIT; -- i1`
39			`i2 : in BIT; -- i2`
40			`q : out BIT; -- q`
41			`vdd : in BIT; -- vdd`
42			`vss : in BIT -- vss`
43			`);`
44			`END COMPONENT;`
45
46			`COMPONENT na2_x1`
47			`port (`
48			`i0 : in BIT; -- i0`
49			`i1 : in BIT; -- i1`
50			`nq : out BIT; -- nq`
51			`vdd : in BIT; -- vdd`
52			`vss : in BIT -- vss`
53			`);`
54			`END COMPONENT;`
55
56			`COMPONENT na3_x1`
57			`port (`
58			`i0 : in BIT; -- i0`
59			`i1 : in BIT; -- i1`
60			`i2 : in BIT; -- i2`
61			`nq : out BIT; -- nq`
62			`vdd : in BIT; -- vdd`
63			`vss : in BIT -- vss`
64			`);`
65			`END COMPONENT;`
66
67			`COMPONENT nao22_x1`
68			`port (`
69			`i0 : in BIT; -- i0`
70			`i1 : in BIT; -- i1`
71			`i2 : in BIT; -- i2`
72			`nq : out BIT; -- nq`
73			`vdd : in BIT; -- vdd`
74			`vss : in BIT -- vss`
75			`);`
76			`END COMPONENT;`
77
78			`COMPONENT an12_x1`
79			`port (`
80			`i0 : in BIT; -- i0`
81			`i1 : in BIT; -- i1`
82			`q : out BIT; -- q`
83			`vdd : in BIT; -- vdd`
84			`vss : in BIT -- vss`
85			`);`
86			`END COMPONENT;`
87
88			`COMPONENT o2_x2`
89			`port (`
90			`i0 : in BIT; -- i0`
91			`i1 : in BIT; -- i1`
92			`q : out BIT; -- q`
93			`vdd : in BIT; -- vdd`
94			`vss : in BIT -- vss`
95			`);`
96			`END COMPONENT;`
97
98			`COMPONENT no3_x1`
99			`port (`
100			`i0 : in BIT; -- i0`
101			`i1 : in BIT; -- i1`
102			`i2 : in BIT; -- i2`
103			`nq : out BIT; -- nq`
104			`vdd : in BIT; -- vdd`
105			`vss : in BIT -- vss`
106			`);`
107			`END COMPONENT;`
108
109			`COMPONENT xr2_x1`
110			`port (`
111			`i0 : in BIT; -- i0`
112			`i1 : in BIT; -- i1`
113			`q : out BIT; -- q`
114			`vdd : in BIT; -- vdd`
115			`vss : in BIT -- vss`
116			`);`
117			`END COMPONENT;`
118
119			`COMPONENT inv_x1`
120			`port (`
121			`i : in BIT; -- i`
122			`nq : out BIT; -- nq`
123			`vdd : in BIT; -- vdd`
124			`vss : in BIT -- vss`
125			`);`
126			`END COMPONENT;`
127
128			`COMPONENT a2_x2`
129			`port (`
130			`i0 : in BIT; -- i0`
131			`i1 : in BIT; -- i1`
132			`q : out BIT; -- q`
133			`vdd : in BIT; -- vdd`
134			`vss : in BIT -- vss`
135			`);`
136			`END COMPONENT;`
137
138			`COMPONENT a3_x2`
139			`port (`
140			`i0 : in BIT; -- i0`
141			`i1 : in BIT; -- i1`
142			`i2 : in BIT; -- i2`
143			`q : out BIT; -- q`
144			`vdd : in BIT; -- vdd`
145			`vss : in BIT -- vss`
146			`);`
147			`END COMPONENT;`
148
149			`COMPONENT sff1_x4`
150			`port (`
151			`ck : in BIT; -- ck`
152			`i : in BIT; -- i`
153			`q : out BIT; -- q`
154			`vdd : in BIT; -- vdd`
155			`vss : in BIT -- vss`
156			`);`
157			`END COMPONENT;`
158
159			`SIGNAL auxsc11 : BIT; -- auxsc11`
160			`SIGNAL auxsc12 : BIT; -- auxsc12`
161			`SIGNAL auxsc15 : BIT; -- auxsc15`
162			`SIGNAL auxsc21 : BIT; -- auxsc21`
163			`SIGNAL auxsc19 : BIT; -- auxsc19`
164			`SIGNAL auxsc16 : BIT; -- auxsc16`
165			`SIGNAL auxsc20 : BIT; -- auxsc20`
166			`SIGNAL auxsc32 : BIT; -- auxsc32`
167			`SIGNAL auxsc8 : BIT; -- auxsc8`
168			`SIGNAL auxsc33 : BIT; -- auxsc33`
169			`SIGNAL auxsc34 : BIT; -- auxsc34`
170			`SIGNAL auxsc35 : BIT; -- auxsc35`
171			`SIGNAL auxsc36 : BIT; -- auxsc36`
172			`SIGNAL auxsc43 : BIT; -- auxsc43`
173			`SIGNAL auxsc44 : BIT; -- auxsc44`
174			`SIGNAL auxsc45 : BIT; -- auxsc45`
175			`SIGNAL auxsc46 : BIT; -- auxsc46`
176			`SIGNAL auxsc47 : BIT; -- auxsc47`
177			`SIGNAL auxsc48 : BIT; -- auxsc48`
178			`SIGNAL auxsc9 : BIT; -- auxsc9`
179			`SIGNAL auxsc10 : BIT; -- auxsc10`
180			`SIGNAL auxsc6 : BIT; -- auxsc6`
181			`SIGNAL auxreg3 : BIT; -- auxreg3`
182			`SIGNAL auxreg2 : BIT; -- auxreg2`
183			`SIGNAL auxreg1 : BIT; -- auxreg1`
184
185			`BEGIN`
186
187			`cp_sended : nao22_x1`
188			`PORT MAP (`
189			`vss => vss,`
190			`vdd => vdd,`
191			`nq => cp_sended,`
192			`i2 => auxsc36,`
193			`i1 => auxsc33,`
194			`i0 => rst);`
195			`req_cp : on12_x1`
196			`PORT MAP (`
197			`vss => vss,`
198			`vdd => vdd,`
199			`q => req_cp,`
200			`i1 => auxsc48,`
201			`i0 => auxsc11);`
202			`auxsc6 : nao22_x1`
203			`PORT MAP (`
204			`vss => vss,`
205			`vdd => vdd,`
206			`nq => auxsc6,`
207			`i2 => auxsc10,`
208			`i1 => auxsc9,`
209			`i0 => rst);`
210			`auxsc10 : o3_x2`
211			`PORT MAP (`
212			`vss => vss,`
213			`vdd => vdd,`
214			`q => auxsc10,`
215			`i2 => rst,`
216			`i1 => emp_bufout,`
217			`i0 => auxsc8);`
218			`auxsc9 : na2_x1`
219			`PORT MAP (`
220			`vss => vss,`
221			`vdd => vdd,`
222			`nq => auxsc9,`
223			`i1 => auxreg3,`
224			`i0 => auxreg2);`
225			`auxsc48 : nao22_x1`
226			`PORT MAP (`
227			`vss => vss,`
228			`vdd => vdd,`
229			`nq => auxsc48,`
230			`i2 => auxsc47,`
231			`i1 => auxreg3,`
232			`i0 => auxsc44);`
233			`auxsc47 : inv_x1`
234			`PORT MAP (`
235			`vss => vss,`
236			`vdd => vdd,`
237			`nq => auxsc47,`
238			`i => auxsc46);`
239			`auxsc46 : an12_x1`
240			`PORT MAP (`
241			`vss => vss,`
242			`vdd => vdd,`
243			`q => auxsc46,`
244			`i1 => auxreg1,`
245			`i0 => auxsc45);`
246			`auxsc45 : inv_x1`
247			`PORT MAP (`
248			`vss => vss,`
249			`vdd => vdd,`
250			`nq => auxsc45,`
251			`i => emp_bufout);`
252			`auxsc44 : na3_x1`
253			`PORT MAP (`
254			`vss => vss,`
255			`vdd => vdd,`
256			`nq => auxsc44,`
257			`i2 => auxsc43,`
258			`i1 => auxsc8,`
259			`i0 => auxsc21);`
260			`auxsc43 : inv_x1`
261			`PORT MAP (`
262			`vss => vss,`
263			`vdd => vdd,`
264			`nq => auxsc43,`
265			`i => auxreg2);`
266			`auxsc36 : inv_x1`
267			`PORT MAP (`
268			`vss => vss,`
269			`vdd => vdd,`
270			`nq => auxsc36,`
271			`i => auxsc35);`
272			`auxsc35 : an12_x1`
273			`PORT MAP (`
274			`vss => vss,`
275			`vdd => vdd,`
276			`q => auxsc35,`
277			`i1 => auxsc34,`
278			`i0 => rst);`
279			`auxsc34 : an12_x1`
280			`PORT MAP (`
281			`vss => vss,`
282			`vdd => vdd,`
283			`q => auxsc34,`
284			`i1 => auxreg1,`
285			`i0 => emp_bufout);`
286			`auxsc33 : nao22_x1`
287			`PORT MAP (`
288			`vss => vss,`
289			`vdd => vdd,`
290			`nq => auxsc33,`
291			`i2 => auxsc8,`
292			`i1 => auxreg3,`
293			`i0 => auxsc32);`
294			`auxsc8 : inv_x1`
295			`PORT MAP (`
296			`vss => vss,`
297			`vdd => vdd,`
298			`nq => auxsc8,`
299			`i => auxreg1);`
300			`auxsc32 : an12_x1`
301			`PORT MAP (`
302			`vss => vss,`
303			`vdd => vdd,`
304			`q => auxsc32,`
305			`i1 => auxreg2,`
306			`i0 => emp_bufout);`
307			`auxsc20 : o2_x2`
308			`PORT MAP (`
309			`vss => vss,`
310			`vdd => vdd,`
311			`q => auxsc20,`
312			`i1 => auxsc16,`
313			`i0 => auxsc19);`
314			`auxsc16 : a2_x2`
315			`PORT MAP (`
316			`vss => vss,`
317			`vdd => vdd,`
318			`q => auxsc16,`
319			`i1 => auxreg2,`
320			`i0 => emp_bufout);`
321			`auxsc19 : no3_x1`
322			`PORT MAP (`
323			`vss => vss,`
324			`vdd => vdd,`
325			`nq => auxsc19,`
326			`i2 => auxreg2,`
327			`i1 => auxreg1,`
328			`i0 => auxsc21);`
329			`auxsc21 : inv_x1`
330			`PORT MAP (`
331			`vss => vss,`
332			`vdd => vdd,`
333			`nq => auxsc21,`
334			`i => cp_ready);`
335			`auxsc15 : inv_x1`
336			`PORT MAP (`
337			`vss => vss,`
338			`vdd => vdd,`
339			`nq => auxsc15,`
340			`i => auxreg3);`
341			`auxsc12 : xr2_x1`
342			`PORT MAP (`
343			`vss => vss,`
344			`vdd => vdd,`
345			`q => auxsc12,`
346			`i1 => auxreg3,`
347			`i0 => auxreg2);`
348			`auxsc11 : inv_x1`
349			`PORT MAP (`
350			`vss => vss,`
351			`vdd => vdd,`
352			`nq => auxsc11,`
353			`i => rst);`
354			`auxinit1_a : a2_x2`
355			`PORT MAP (`
356			`vss => vss,`
357			`vdd => vdd,`
358			`q => n_block,`
359			`i1 => auxsc12,`
360			`i0 => auxsc11);`
361			`auxinit2_a : a3_x2`
362			`PORT MAP (`
363			`vss => vss,`
364			`vdd => vdd,`
365			`q => en_bufout,`
366			`i2 => auxsc20,`
367			`i1 => auxsc11,`
368			`i0 => auxsc15);`
369			`current_state_0 : sff1_x4`
370			`PORT MAP (`
371			`vss => vss,`
372			`vdd => vdd,`
373			`q => auxreg1,`
374			`i => auxsc6,`
375			`ck => clk);`
376			`current_state_1 : sff1_x4`
377			`PORT MAP (`
378			`vss => vss,`
379			`vdd => vdd,`
380			`q => auxreg2,`
381			`i => n_block,`
382			`ck => clk);`
383			`current_state_2 : sff1_x4`
384			`PORT MAP (`
385			`vss => vss,`
386			`vdd => vdd,`
387			`q => auxreg3,`
388			`i => en_bufout,`
389			`ck => clk);`
390
391			`end VST;`