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-- VHDL structural description generated from `count3_latch`

--              date : Thu Aug  2 10:00:10 2001

-- Entity Declaration

ENTITY count3_latch IS

  PORT (

  clk : in BIT; -- clk

  en : in BIT;  -- en

  rst : in BIT; -- rst

  q : out BIT_VECTOR (2 DOWNTO 0);      -- q

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END count3_latch;

-- Architecture Declaration

ARCHITECTURE VST OF count3_latch IS

  COMPONENT count3

    port (

    clk : in BIT;       -- clk

    rst : in BIT;       -- rst

    q : out BIT_VECTOR(2 DOWNTO 0);     -- q

    vdd : in BIT;       -- vdd

    vss : in BIT        -- vss

    );

  END COMPONENT;

  COMPONENT latch

    port (

    a : in BIT; -- a

    en : in BIT;        -- en

    b : inout BIT;      -- b

    vdd : in BIT;       -- vdd

    vss : in BIT        -- vss

    );

  END COMPONENT;

  SIGNAL p_0 : BIT;     -- p 0

  SIGNAL p_1 : BIT;     -- p 1

  SIGNAL p_2 : BIT;     -- p 2

  SIGNAL vd : BIT;      -- vd

BEGIN

  count1 : count3

    PORT MAP (

    vss => vss,

    vdd => vd,

    q => p_2& p_1& p_0,

    rst => rst,

    clk => clk);

  latch0 : latch

    PORT MAP (

    vss => vss,

    vdd => vdd,

    b => q(0),

    en => en,

    a => p_0);

  latch1 : latch

    PORT MAP (

    vss => vss,

    vdd => vdd,

    b => q(1),

    en => en,

    a => p_1);

  latch2 : latch

    PORT MAP (

    vss => vss,

    vdd => vdd,

    b => q(2),

    en => en,

    a => p_2);

end VST;