URL https://opencores.org/ocsvn/structural_vhdl/structural_vhdl/trunk

Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [tags/] [vlsi/] [key_regulator/] [count4_latch.vst] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


-- VHDL structural description generated from `count4_latch`
--              date : Thu Aug  2 10:03:29 2001
 
 
-- Entity Declaration
 
ENTITY count4_latch IS
  PORT (
  clk : in BIT; -- clk
  en : in BIT;  -- en
  rst : in BIT; -- rst
  q : out BIT_VECTOR (3 DOWNTO 0);      -- q
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END count4_latch;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF count4_latch IS
  COMPONENT count4
    port (
    clk : in BIT;       -- clk
    rst : in BIT;       -- rst
    q : out BIT_VECTOR(3 DOWNTO 0);     -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT latch
    port (
    a : in BIT; -- a
    en : in BIT;        -- en
    b : inout BIT;      -- b
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL p_0 : BIT;     -- p 0
  SIGNAL p_1 : BIT;     -- p 1
  SIGNAL p_2 : BIT;     -- p 2
  SIGNAL p_3 : BIT;     -- p 3
  SIGNAL vd : BIT;      -- vd
 
BEGIN
 
  count1 : count4
    PORT MAP (
    vss => vss,
    vdd => vd,
    q => p_3& p_2& p_1& p_0,
    rst => rst,
    clk => clk);
  latch0 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => q(0),
    en => en,
    a => p_0);
  latch1 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => q(1),
    en => en,
    a => p_1);
  latch2 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => q(2),
    en => en,
    a => p_2);
  latch3 : latch
    PORT MAP (
    vss => vss,
    vdd => vdd,
    b => q(3),
    en => en,
    a => p_3);
 
end VST;

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `count4_latch`
2			`-- date : Thu Aug 2 10:03:29 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY count4_latch IS`
8			`PORT (`
9			`clk : in BIT; -- clk`
10			`en : in BIT; -- en`
11			`rst : in BIT; -- rst`
12			`q : out BIT_VECTOR (3 DOWNTO 0); -- q`
13			`vdd : in BIT; -- vdd`
14			`vss : in BIT -- vss`
15			`);`
16			`END count4_latch;`
17
18			`-- Architecture Declaration`
19
20			`ARCHITECTURE VST OF count4_latch IS`
21			`COMPONENT count4`
22			`port (`
23			`clk : in BIT; -- clk`
24			`rst : in BIT; -- rst`
25			`q : out BIT_VECTOR(3 DOWNTO 0); -- q`
26			`vdd : in BIT; -- vdd`
27			`vss : in BIT -- vss`
28			`);`
29			`END COMPONENT;`
30
31			`COMPONENT latch`
32			`port (`
33			`a : in BIT; -- a`
34			`en : in BIT; -- en`
35			`b : inout BIT; -- b`
36			`vdd : in BIT; -- vdd`
37			`vss : in BIT -- vss`
38			`);`
39			`END COMPONENT;`
40
41			`SIGNAL p_0 : BIT; -- p 0`
42			`SIGNAL p_1 : BIT; -- p 1`
43			`SIGNAL p_2 : BIT; -- p 2`
44			`SIGNAL p_3 : BIT; -- p 3`
45			`SIGNAL vd : BIT; -- vd`
46
47			`BEGIN`
48
49			`count1 : count4`
50			`PORT MAP (`
51			`vss => vss,`
52			`vdd => vd,`
53			`q => p_3& p_2& p_1& p_0,`
54			`rst => rst,`
55			`clk => clk);`
56			`latch0 : latch`
57			`PORT MAP (`
58			`vss => vss,`
59			`vdd => vdd,`
60			`b => q(0),`
61			`en => en,`
62			`a => p_0);`
63			`latch1 : latch`
64			`PORT MAP (`
65			`vss => vss,`
66			`vdd => vdd,`
67			`b => q(1),`
68			`en => en,`
69			`a => p_1);`
70			`latch2 : latch`
71			`PORT MAP (`
72			`vss => vss,`
73			`vdd => vdd,`
74			`b => q(2),`
75			`en => en,`
76			`a => p_2);`
77			`latch3 : latch`
78			`PORT MAP (`
79			`vss => vss,`
80			`vdd => vdd,`
81			`b => q(3),`
82			`en => en,`
83			`a => p_3);`
84
85			`end VST;`

Browse

Tools

Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [tags/] [vlsi/] [key_regulator/] [count4_latch.vst] - Blame information for rev 2