OpenCores
URL https://opencores.org/ocsvn/structural_vhdl/structural_vhdl/trunk

Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [tags/] [vlsi/] [key_regulator/] [fulladder16.vst] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 marta 
-- VHDL structural description generated from `fulladder16`
2 
--              date : Tue Jul 31 11:58:00 2001
3 
 
4 
 
5 
-- Entity Declaration
6 
 
7 
ENTITY fulladder16 IS
8 
  PORT (
9 
  a : in BIT_VECTOR (15 DOWNTO 0);      -- a
10 
  b : in BIT_VECTOR (15 DOWNTO 0);      -- b
11 
  sum : out BIT_VECTOR (15 DOWNTO 0);   -- sum
12 
  vdd : in BIT; -- vdd
13 
  vss : in BIT  -- vss
14 
  );
15 
END fulladder16;
16 
 
17 
-- Architecture Declaration
18 
 
19 
ARCHITECTURE VST OF fulladder16 IS
20 
  COMPONENT zero_x0
21 
    port (
22 
    nq : out BIT;       -- nq
23 
    vdd : in BIT;       -- vdd
24 
    vss : in BIT        -- vss
25 
    );
26 
  END COMPONENT;
27 
 
28 
  COMPONENT fulladder
29 
    port (
30 
    a : in BIT; -- a
31 
    b : in BIT; -- b
32 
    cin : in BIT;       -- cin
33 
    sum : out BIT;      -- sum
34 
    cout : out BIT;     -- cout
35 
    vdd : in BIT;       -- vdd
36 
    vss : in BIT        -- vss
37 
    );
38 
  END COMPONENT;
39 
 
40 
  COMPONENT fulladdercout
41 
    port (
42 
    a : in BIT; -- a
43 
    b : in BIT; -- b
44 
    cin : in BIT;       -- cin
45 
    sum : out BIT;      -- sum
46 
    vdd : in BIT;       -- vdd
47 
    vss : in BIT        -- vss
48 
    );
49 
  END COMPONENT;
50 
 
51 
  SIGNAL cout0 : BIT;   -- cout0
52 
  SIGNAL cout1 : BIT;   -- cout1
53 
  SIGNAL cout10 : BIT;  -- cout10
54 
  SIGNAL cout11 : BIT;  -- cout11
55 
  SIGNAL cout12 : BIT;  -- cout12
56 
  SIGNAL cout13 : BIT;  -- cout13
57 
  SIGNAL cout14 : BIT;  -- cout14
58 
  SIGNAL cout2 : BIT;   -- cout2
59 
  SIGNAL cout3 : BIT;   -- cout3
60 
  SIGNAL cout4 : BIT;   -- cout4
61 
  SIGNAL cout5 : BIT;   -- cout5
62 
  SIGNAL cout6 : BIT;   -- cout6
63 
  SIGNAL cout7 : BIT;   -- cout7
64 
  SIGNAL cout8 : BIT;   -- cout8
65 
  SIGNAL cout9 : BIT;   -- cout9
66 
  SIGNAL nol : BIT;     -- nol
67 
 
68 
BEGIN
69 
 
70 
  zero1 : zero_x0
71 
    PORT MAP (
72 
    vss => vss,
73 
    vdd => vdd,
74 
    nq => nol);
75 
  fulladder1 : fulladder
76 
    PORT MAP (
77 
    vss => vss,
78 
    vdd => vdd,
79 
    cout => cout0,
80 
    sum => sum(0),
81 
    cin => nol,
82 
    b => b(0),
83 
    a => a(0));
84 
  fulladder2 : fulladder
85 
    PORT MAP (
86 
    vss => vss,
87 
    vdd => vdd,
88 
    cout => cout1,
89 
    sum => sum(1),
90 
    cin => cout0,
91 
    b => b(1),
92 
    a => a(1));
93 
  fulladder3 : fulladder
94 
    PORT MAP (
95 
    vss => vss,
96 
    vdd => vdd,
97 
    cout => cout2,
98 
    sum => sum(2),
99 
    cin => cout1,
100 
    b => b(2),
101 
    a => a(2));
102 
  fulladder4 : fulladder
103 
    PORT MAP (
104 
    vss => vss,
105 
    vdd => vdd,
106 
    cout => cout3,
107 
    sum => sum(3),
108 
    cin => cout2,
109 
    b => b(3),
110 
    a => a(3));
111 
  fulladder5 : fulladder
112 
    PORT MAP (
113 
    vss => vss,
114 
    vdd => vdd,
115 
    cout => cout4,
116 
    sum => sum(4),
117 
    cin => cout3,
118 
    b => b(4),
119 
    a => a(4));
120 
  fulladder6 : fulladder
121 
    PORT MAP (
122 
    vss => vss,
123 
    vdd => vdd,
124 
    cout => cout5,
125 
    sum => sum(5),
126 
    cin => cout4,
127 
    b => b(5),
128 
    a => a(5));
129 
  fulladder7 : fulladder
130 
    PORT MAP (
131 
    vss => vss,
132 
    vdd => vdd,
133 
    cout => cout6,
134 
    sum => sum(6),
135 
    cin => cout5,
136 
    b => b(6),
137 
    a => a(6));
138 
  fulladder8 : fulladder
139 
    PORT MAP (
140 
    vss => vss,
141 
    vdd => vdd,
142 
    cout => cout7,
143 
    sum => sum(7),
144 
    cin => cout6,
145 
    b => b(7),
146 
    a => a(7));
147 
  fulladder9 : fulladder
148 
    PORT MAP (
149 
    vss => vss,
150 
    vdd => vdd,
151 
    cout => cout8,
152 
    sum => sum(8),
153 
    cin => cout7,
154 
    b => b(8),
155 
    a => a(8));
156 
  fulladder10 : fulladder
157 
    PORT MAP (
158 
    vss => vss,
159 
    vdd => vdd,
160 
    cout => cout9,
161 
    sum => sum(9),
162 
    cin => cout8,
163 
    b => b(9),
164 
    a => a(9));
165 
  fulladder11 : fulladder
166 
    PORT MAP (
167 
    vss => vss,
168 
    vdd => vdd,
169 
    cout => cout10,
170 
    sum => sum(10),
171 
    cin => cout9,
172 
    b => b(10),
173 
    a => a(10));
174 
  fulladder12 : fulladder
175 
    PORT MAP (
176 
    vss => vss,
177 
    vdd => vdd,
178 
    cout => cout11,
179 
    sum => sum(11),
180 
    cin => cout10,
181 
    b => b(11),
182 
    a => a(11));
183 
  fulladder13 : fulladder
184 
    PORT MAP (
185 
    vss => vss,
186 
    vdd => vdd,
187 
    cout => cout12,
188 
    sum => sum(12),
189 
    cin => cout11,
190 
    b => b(12),
191 
    a => a(12));
192 
  fulladder14 : fulladder
193 
    PORT MAP (
194 
    vss => vss,
195 
    vdd => vdd,
196 
    cout => cout13,
197 
    sum => sum(13),
198 
    cin => cout12,
199 
    b => b(13),
200 
    a => a(13));
201 
  fulladder15 : fulladder
202 
    PORT MAP (
203 
    vss => vss,
204 
    vdd => vdd,
205 
    cout => cout14,
206 
    sum => sum(14),
207 
    cin => cout13,
208 
    b => b(14),
209 
    a => a(14));
210 
  fulladder16 : fulladdercout
211 
    PORT MAP (
212 
    vss => vss,
213 
    vdd => vdd,
214 
    sum => sum(15),
215 
    cin => cout14,
216 
    b => b(15),
217 
    a => a(15));
218 
 
219 
end VST;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.