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marta |
-- VHDL structural description generated from `invmuls`
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-- date : Sat Sep 1 20:52:37 2001
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-- Entity Declaration
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ENTITY invmuls IS
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PORT (
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zi : in BIT_VECTOR (15 DOWNTO 0); -- zi
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rst : in BIT; -- rst
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en_pipe : in BIT; -- en_pipe
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sel : in BIT; -- sel
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cke : in BIT; -- cke
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zo : out BIT_VECTOR (15 DOWNTO 0); -- zo
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END invmuls;
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-- Architecture Declaration
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ARCHITECTURE VST OF invmuls IS
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COMPONENT mux16
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port (
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a : in BIT_VECTOR(15 DOWNTO 0); -- a
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b : in BIT_VECTOR(15 DOWNTO 0); -- b
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sel : in BIT; -- sel
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c : out BIT_VECTOR(15 DOWNTO 0); -- c
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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COMPONENT mulmod
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port (
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in1 : in BIT_VECTOR(15 DOWNTO 0); -- in1
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in2 : in BIT_VECTOR(15 DOWNTO 0); -- in2
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en : in BIT; -- en
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rst : in BIT; -- rst
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cke : in BIT; -- cke
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mulout : out BIT_VECTOR(15 DOWNTO 0); -- mulout
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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COMPONENT reg16_latch
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port (
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a : in BIT_VECTOR(15 DOWNTO 0); -- a
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en : in BIT; -- en
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clr : in BIT; -- clr
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cke : in BIT; -- cke
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b : inout BIT_VECTOR(15 DOWNTO 0); -- b
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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SIGNAL clr : BIT; -- clr
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SIGNAL en : BIT; -- en
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SIGNAL o_mux_l_0 : BIT; -- o_mux_l 0
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SIGNAL o_mux_l_1 : BIT; -- o_mux_l 1
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SIGNAL o_mux_l_2 : BIT; -- o_mux_l 2
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SIGNAL o_mux_l_3 : BIT; -- o_mux_l 3
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SIGNAL o_mux_l_4 : BIT; -- o_mux_l 4
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SIGNAL o_mux_l_5 : BIT; -- o_mux_l 5
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SIGNAL o_mux_l_6 : BIT; -- o_mux_l 6
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SIGNAL o_mux_l_7 : BIT; -- o_mux_l 7
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SIGNAL o_mux_l_8 : BIT; -- o_mux_l 8
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SIGNAL o_mux_l_9 : BIT; -- o_mux_l 9
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SIGNAL o_mux_l_10 : BIT; -- o_mux_l 10
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SIGNAL o_mux_l_11 : BIT; -- o_mux_l 11
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SIGNAL o_mux_l_12 : BIT; -- o_mux_l 12
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SIGNAL o_mux_l_13 : BIT; -- o_mux_l 13
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SIGNAL o_mux_l_14 : BIT; -- o_mux_l 14
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SIGNAL o_mux_l_15 : BIT; -- o_mux_l 15
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SIGNAL o_mux_r_0 : BIT; -- o_mux_r 0
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SIGNAL o_mux_r_1 : BIT; -- o_mux_r 1
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SIGNAL o_mux_r_2 : BIT; -- o_mux_r 2
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SIGNAL o_mux_r_3 : BIT; -- o_mux_r 3
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SIGNAL o_mux_r_4 : BIT; -- o_mux_r 4
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SIGNAL o_mux_r_5 : BIT; -- o_mux_r 5
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SIGNAL o_mux_r_6 : BIT; -- o_mux_r 6
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SIGNAL o_mux_r_7 : BIT; -- o_mux_r 7
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SIGNAL o_mux_r_8 : BIT; -- o_mux_r 8
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SIGNAL o_mux_r_9 : BIT; -- o_mux_r 9
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SIGNAL o_mux_r_10 : BIT; -- o_mux_r 10
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SIGNAL o_mux_r_11 : BIT; -- o_mux_r 11
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SIGNAL o_mux_r_12 : BIT; -- o_mux_r 12
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SIGNAL o_mux_r_13 : BIT; -- o_mux_r 13
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SIGNAL o_mux_r_14 : BIT; -- o_mux_r 14
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SIGNAL o_mux_r_15 : BIT; -- o_mux_r 15
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SIGNAL ost1_l_0 : BIT; -- ost1_l 0
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SIGNAL ost1_l_1 : BIT; -- ost1_l 1
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SIGNAL ost1_l_2 : BIT; -- ost1_l 2
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SIGNAL ost1_l_3 : BIT; -- ost1_l 3
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SIGNAL ost1_l_4 : BIT; -- ost1_l 4
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SIGNAL ost1_l_5 : BIT; -- ost1_l 5
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SIGNAL ost1_l_6 : BIT; -- ost1_l 6
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SIGNAL ost1_l_7 : BIT; -- ost1_l 7
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SIGNAL ost1_l_8 : BIT; -- ost1_l 8
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SIGNAL ost1_l_9 : BIT; -- ost1_l 9
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SIGNAL ost1_l_10 : BIT; -- ost1_l 10
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SIGNAL ost1_l_11 : BIT; -- ost1_l 11
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SIGNAL ost1_l_12 : BIT; -- ost1_l 12
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SIGNAL ost1_l_13 : BIT; -- ost1_l 13
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SIGNAL ost1_l_14 : BIT; -- ost1_l 14
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SIGNAL ost1_l_15 : BIT; -- ost1_l 15
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SIGNAL ost1_r_0 : BIT; -- ost1_r 0
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SIGNAL ost1_r_1 : BIT; -- ost1_r 1
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SIGNAL ost1_r_2 : BIT; -- ost1_r 2
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SIGNAL ost1_r_3 : BIT; -- ost1_r 3
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SIGNAL ost1_r_4 : BIT; -- ost1_r 4
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SIGNAL ost1_r_5 : BIT; -- ost1_r 5
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SIGNAL ost1_r_6 : BIT; -- ost1_r 6
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SIGNAL ost1_r_7 : BIT; -- ost1_r 7
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SIGNAL ost1_r_8 : BIT; -- ost1_r 8
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SIGNAL ost1_r_9 : BIT; -- ost1_r 9
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SIGNAL ost1_r_10 : BIT; -- ost1_r 10
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SIGNAL ost1_r_11 : BIT; -- ost1_r 11
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SIGNAL ost1_r_12 : BIT; -- ost1_r 12
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SIGNAL ost1_r_13 : BIT; -- ost1_r 13
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SIGNAL ost1_r_14 : BIT; -- ost1_r 14
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SIGNAL ost1_r_15 : BIT; -- ost1_r 15
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SIGNAL ost2_l_0 : BIT; -- ost2_l 0
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SIGNAL ost2_l_1 : BIT; -- ost2_l 1
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SIGNAL ost2_l_2 : BIT; -- ost2_l 2
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SIGNAL ost2_l_3 : BIT; -- ost2_l 3
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SIGNAL ost2_l_4 : BIT; -- ost2_l 4
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SIGNAL ost2_l_5 : BIT; -- ost2_l 5
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SIGNAL ost2_l_6 : BIT; -- ost2_l 6
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SIGNAL ost2_l_7 : BIT; -- ost2_l 7
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SIGNAL ost2_l_8 : BIT; -- ost2_l 8
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SIGNAL ost2_l_9 : BIT; -- ost2_l 9
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SIGNAL ost2_l_10 : BIT; -- ost2_l 10
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SIGNAL ost2_l_11 : BIT; -- ost2_l 11
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SIGNAL ost2_l_12 : BIT; -- ost2_l 12
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SIGNAL ost2_l_13 : BIT; -- ost2_l 13
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SIGNAL ost2_l_14 : BIT; -- ost2_l 14
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SIGNAL ost2_l_15 : BIT; -- ost2_l 15
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SIGNAL ost2_r_0 : BIT; -- ost2_r 0
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SIGNAL ost2_r_1 : BIT; -- ost2_r 1
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SIGNAL ost2_r_2 : BIT; -- ost2_r 2
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SIGNAL ost2_r_3 : BIT; -- ost2_r 3
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SIGNAL ost2_r_4 : BIT; -- ost2_r 4
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SIGNAL ost2_r_5 : BIT; -- ost2_r 5
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SIGNAL ost2_r_6 : BIT; -- ost2_r 6
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SIGNAL ost2_r_7 : BIT; -- ost2_r 7
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SIGNAL ost2_r_8 : BIT; -- ost2_r 8
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SIGNAL ost2_r_9 : BIT; -- ost2_r 9
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SIGNAL ost2_r_10 : BIT; -- ost2_r 10
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SIGNAL ost2_r_11 : BIT; -- ost2_r 11
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SIGNAL ost2_r_12 : BIT; -- ost2_r 12
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SIGNAL ost2_r_13 : BIT; -- ost2_r 13
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SIGNAL ost2_r_14 : BIT; -- ost2_r 14
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SIGNAL ost2_r_15 : BIT; -- ost2_r 15
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SIGNAL ost3_r_0 : BIT; -- ost3_r 0
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SIGNAL ost3_r_1 : BIT; -- ost3_r 1
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SIGNAL ost3_r_2 : BIT; -- ost3_r 2
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SIGNAL ost3_r_3 : BIT; -- ost3_r 3
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SIGNAL ost3_r_4 : BIT; -- ost3_r 4
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SIGNAL ost3_r_5 : BIT; -- ost3_r 5
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SIGNAL ost3_r_6 : BIT; -- ost3_r 6
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SIGNAL ost3_r_7 : BIT; -- ost3_r 7
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SIGNAL ost3_r_8 : BIT; -- ost3_r 8
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SIGNAL ost3_r_9 : BIT; -- ost3_r 9
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SIGNAL ost3_r_10 : BIT; -- ost3_r 10
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SIGNAL ost3_r_11 : BIT; -- ost3_r 11
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SIGNAL ost3_r_12 : BIT; -- ost3_r 12
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SIGNAL ost3_r_13 : BIT; -- ost3_r 13
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SIGNAL ost3_r_14 : BIT; -- ost3_r 14
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SIGNAL ost3_r_15 : BIT; -- ost3_r 15
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BEGIN
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mux_l : mux16
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PORT MAP (
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vss => vss,
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vdd => vdd,
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c => o_mux_l_15& o_mux_l_14& o_mux_l_13& o_mux_l_12& o_mux_l_11& o_mux_l_10& o_mux_l_9& o_mux_l_8& o_mux_l_7& o_mux_l_6& o_mux_l_5& o_mux_l_4& o_mux_l_3& o_mux_l_2& o_mux_l_1& o_mux_l_0,
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sel => sel,
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b => zi(15)& zi(14)& zi(13)& zi(12)& zi(11)& zi(10)& zi(9)& zi(8)& zi(7)& zi(6)& zi(5)& zi(4)& zi(3)& zi(2)& zi(1)& zi(0),
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a => zo(15)& zo(14)& zo(13)& zo(12)& zo(11)& zo(10)& zo(9)& zo(8)& zo(7)& zo(6)& zo(5)& zo(4)& zo(3)& zo(2)& zo(1)& zo(0));
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mux_r : mux16
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PORT MAP (
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vss => vss,
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vdd => vdd,
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c => o_mux_r_15& o_mux_r_14& o_mux_r_13& o_mux_r_12& o_mux_r_11& o_mux_r_10& o_mux_r_9& o_mux_r_8& o_mux_r_7& o_mux_r_6& o_mux_r_5& o_mux_r_4& o_mux_r_3& o_mux_r_2& o_mux_r_1& o_mux_r_0,
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sel => sel,
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b => zi(15)& zi(14)& zi(13)& zi(12)& zi(11)& zi(10)& zi(9)& zi(8)& zi(7)& zi(6)& zi(5)& zi(4)& zi(3)& zi(2)& zi(1)& zi(0),
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a => ost3_r_15& ost3_r_14& ost3_r_13& ost3_r_12& ost3_r_11& ost3_r_10& ost3_r_9& ost3_r_8& ost3_r_7& ost3_r_6& ost3_r_5& ost3_r_4& ost3_r_3& ost3_r_2& ost3_r_1& ost3_r_0);
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reg1_l : reg16_latch
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PORT MAP (
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vss => vss,
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vdd => vdd,
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b => ost1_l_15& ost1_l_14& ost1_l_13& ost1_l_12& ost1_l_11& ost1_l_10& ost1_l_9& ost1_l_8& ost1_l_7& ost1_l_6& ost1_l_5& ost1_l_4& ost1_l_3& ost1_l_2& ost1_l_1& ost1_l_0,
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cke => cke,
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clr => clr,
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en => en,
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a => o_mux_l_15& o_mux_l_14& o_mux_l_13& o_mux_l_12& o_mux_l_11& o_mux_l_10& o_mux_l_9& o_mux_l_8& o_mux_l_7& o_mux_l_6& o_mux_l_5& o_mux_l_4& o_mux_l_3& o_mux_l_2& o_mux_l_1& o_mux_l_0);
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reg1_r : reg16_latch
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PORT MAP (
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vss => vss,
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vdd => vdd,
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| 205 |
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b => ost1_r_15& ost1_r_14& ost1_r_13& ost1_r_12& ost1_r_11& ost1_r_10& ost1_r_9& ost1_r_8& ost1_r_7& ost1_r_6& ost1_r_5& ost1_r_4& ost1_r_3& ost1_r_2& ost1_r_1& ost1_r_0,
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| 206 |
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cke => cke,
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| 207 |
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clr => clr,
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| 208 |
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en => en,
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| 209 |
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a => o_mux_r_15& o_mux_r_14& o_mux_r_13& o_mux_r_12& o_mux_r_11& o_mux_r_10& o_mux_r_9& o_mux_r_8& o_mux_r_7& o_mux_r_6& o_mux_r_5& o_mux_r_4& o_mux_r_3& o_mux_r_2& o_mux_r_1& o_mux_r_0);
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| 210 |
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reg2_l : reg16_latch
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| 211 |
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PORT MAP (
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| 212 |
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vss => vss,
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| 213 |
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vdd => vdd,
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| 214 |
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b => ost2_l_15& ost2_l_14& ost2_l_13& ost2_l_12& ost2_l_11& ost2_l_10& ost2_l_9& ost2_l_8& ost2_l_7& ost2_l_6& ost2_l_5& ost2_l_4& ost2_l_3& ost2_l_2& ost2_l_1& ost2_l_0,
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| 215 |
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cke => cke,
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| 216 |
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clr => clr,
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| 217 |
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en => en,
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| 218 |
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a => ost1_l_15& ost1_l_14& ost1_l_13& ost1_l_12& ost1_l_11& ost1_l_10& ost1_l_9& ost1_l_8& ost1_l_7& ost1_l_6& ost1_l_5& ost1_l_4& ost1_l_3& ost1_l_2& ost1_l_1& ost1_l_0);
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| 219 |
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mulmod_r : mulmod
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| 220 |
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PORT MAP (
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| 221 |
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vss => vss,
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| 222 |
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vdd => vdd,
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| 223 |
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mulout => ost2_r_15& ost2_r_14& ost2_r_13& ost2_r_12& ost2_r_11& ost2_r_10& ost2_r_9& ost2_r_8& ost2_r_7& ost2_r_6& ost2_r_5& ost2_r_4& ost2_r_3& ost2_r_2& ost2_r_1& ost2_r_0,
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| 224 |
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cke => cke,
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| 225 |
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rst => clr,
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| 226 |
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en => en,
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| 227 |
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in2 => ost1_r_15& ost1_r_14& ost1_r_13& ost1_r_12& ost1_r_11& ost1_r_10& ost1_r_9& ost1_r_8& ost1_r_7& ost1_r_6& ost1_r_5& ost1_r_4& ost1_r_3& ost1_r_2& ost1_r_1& ost1_r_0,
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| 228 |
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in1 => ost1_r_15& ost1_r_14& ost1_r_13& ost1_r_12& ost1_r_11& ost1_r_10& ost1_r_9& ost1_r_8& ost1_r_7& ost1_r_6& ost1_r_5& ost1_r_4& ost1_r_3& ost1_r_2& ost1_r_1& ost1_r_0);
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| 229 |
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mulmod_l : mulmod
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| 230 |
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PORT MAP (
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| 231 |
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vss => vss,
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| 232 |
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vdd => vdd,
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| 233 |
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mulout => zo(15)& zo(14)& zo(13)& zo(12)& zo(11)& zo(10)& zo(9)& zo(8)& zo(7)& zo(6)& zo(5)& zo(4)& zo(3)& zo(2)& zo(1)& zo(0),
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| 234 |
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cke => cke,
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| 235 |
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rst => clr,
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| 236 |
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en => en,
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| 237 |
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|
in2 => ost2_r_15& ost2_r_14& ost2_r_13& ost2_r_12& ost2_r_11& ost2_r_10& ost2_r_9& ost2_r_8& ost2_r_7& ost2_r_6& ost2_r_5& ost2_r_4& ost2_r_3& ost2_r_2& ost2_r_1& ost2_r_0,
|
| 238 |
|
|
in1 => ost2_l_15& ost2_l_14& ost2_l_13& ost2_l_12& ost2_l_11& ost2_l_10& ost2_l_9& ost2_l_8& ost2_l_7& ost2_l_6& ost2_l_5& ost2_l_4& ost2_l_3& ost2_l_2& ost2_l_1& ost2_l_0);
|
| 239 |
|
|
reg2_r : reg16_latch
|
| 240 |
|
|
PORT MAP (
|
| 241 |
|
|
vss => vss,
|
| 242 |
|
|
vdd => vdd,
|
| 243 |
|
|
b => ost3_r_15& ost3_r_14& ost3_r_13& ost3_r_12& ost3_r_11& ost3_r_10& ost3_r_9& ost3_r_8& ost3_r_7& ost3_r_6& ost3_r_5& ost3_r_4& ost3_r_3& ost3_r_2& ost3_r_1& ost3_r_0,
|
| 244 |
|
|
cke => cke,
|
| 245 |
|
|
clr => clr,
|
| 246 |
|
|
en => en,
|
| 247 |
|
|
a => ost2_r_15& ost2_r_14& ost2_r_13& ost2_r_12& ost2_r_11& ost2_r_10& ost2_r_9& ost2_r_8& ost2_r_7& ost2_r_6& ost2_r_5& ost2_r_4& ost2_r_3& ost2_r_2& ost2_r_1& ost2_r_0);
|
| 248 |
|
|
|
| 249 |
|
|
end VST;
|
