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[/] [structural_vhdl/] [tags/] [vlsi/] [key_regulator/] [leftshiftregister0.vst] - Blame information for rev 4

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-- VHDL structural description generated from `leftshiftregister0`
--              date : Tue Jul 31 10:15:35 2001
 
 
-- Entity Declaration
 
ENTITY leftshiftregister0 IS
  PORT (
  p : in BIT_VECTOR (16 DOWNTO 0);      -- p
  q : in BIT;   -- q
  r : out BIT_VECTOR (33 DOWNTO 0);     -- r
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END leftshiftregister0;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF leftshiftregister0 IS
  COMPONENT a2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT zero_x0
    port (
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
 
BEGIN
 
  r_0 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(0),
    i1 => p(0),
    i0 => q);
  r_1 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(1),
    i1 => p(1),
    i0 => q);
  r_2 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(2),
    i1 => p(2),
    i0 => q);
  r_3 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(3),
    i1 => p(3),
    i0 => q);
  r_4 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(4),
    i1 => p(4),
    i0 => q);
  r_5 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(5),
    i1 => p(5),
    i0 => q);
  r_6 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(6),
    i1 => p(6),
    i0 => q);
  r_7 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(7),
    i1 => p(7),
    i0 => q);
  r_8 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(8),
    i1 => p(8),
    i0 => q);
  r_9 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(9),
    i1 => p(9),
    i0 => q);
  r_10 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(10),
    i1 => p(10),
    i0 => q);
  r_11 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(11),
    i1 => p(11),
    i0 => q);
  r_12 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(12),
    i1 => p(12),
    i0 => q);
  r_13 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(13),
    i1 => p(13),
    i0 => q);
  r_14 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(14),
    i1 => p(14),
    i0 => q);
  r_15 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(15),
    i1 => p(15),
    i0 => q);
  r_16 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(16),
    i1 => p(16),
    i0 => q);
  r_17 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(17));
  r_18 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(18));
  r_19 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(19));
  r_20 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(20));
  r_21 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(21));
  r_22 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(22));
  r_23 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(23));
  r_24 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(24));
  r_25 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(25));
  r_26 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(26));
  r_27 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(27));
  r_28 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(28));
  r_29 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(29));
  r_30 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(30));
  r_31 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(31));
  r_32 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(32));
  r_33 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(33));
 
end VST;

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[/] [structural_vhdl/] [tags/] [vlsi/] [key_regulator/] [leftshiftregister0.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `leftshiftregister0`
2			`-- date : Tue Jul 31 10:15:35 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY leftshiftregister0 IS`
8			`PORT (`
9			`p : in BIT_VECTOR (16 DOWNTO 0); -- p`
10			`q : in BIT; -- q`
11			`r : out BIT_VECTOR (33 DOWNTO 0); -- r`
12			`vdd : in BIT; -- vdd`
13			`vss : in BIT -- vss`
14			`);`
15			`END leftshiftregister0;`
16
17			`-- Architecture Declaration`
18
19			`ARCHITECTURE VST OF leftshiftregister0 IS`
20			`COMPONENT a2_x2`
21			`port (`
22			`i0 : in BIT; -- i0`
23			`i1 : in BIT; -- i1`
24			`q : out BIT; -- q`
25			`vdd : in BIT; -- vdd`
26			`vss : in BIT -- vss`
27			`);`
28			`END COMPONENT;`
29
30			`COMPONENT zero_x0`
31			`port (`
32			`nq : out BIT; -- nq`
33			`vdd : in BIT; -- vdd`
34			`vss : in BIT -- vss`
35			`);`
36			`END COMPONENT;`
37
38
39			`BEGIN`
40
41			`r_0 : a2_x2`
42			`PORT MAP (`
43			`vss => vss,`
44			`vdd => vdd,`
45			`q => r(0),`
46			`i1 => p(0),`
47			`i0 => q);`
48			`r_1 : a2_x2`
49			`PORT MAP (`
50			`vss => vss,`
51			`vdd => vdd,`
52			`q => r(1),`
53			`i1 => p(1),`
54			`i0 => q);`
55			`r_2 : a2_x2`
56			`PORT MAP (`
57			`vss => vss,`
58			`vdd => vdd,`
59			`q => r(2),`
60			`i1 => p(2),`
61			`i0 => q);`
62			`r_3 : a2_x2`
63			`PORT MAP (`
64			`vss => vss,`
65			`vdd => vdd,`
66			`q => r(3),`
67			`i1 => p(3),`
68			`i0 => q);`
69			`r_4 : a2_x2`
70			`PORT MAP (`
71			`vss => vss,`
72			`vdd => vdd,`
73			`q => r(4),`
74			`i1 => p(4),`
75			`i0 => q);`
76			`r_5 : a2_x2`
77			`PORT MAP (`
78			`vss => vss,`
79			`vdd => vdd,`
80			`q => r(5),`
81			`i1 => p(5),`
82			`i0 => q);`
83			`r_6 : a2_x2`
84			`PORT MAP (`
85			`vss => vss,`
86			`vdd => vdd,`
87			`q => r(6),`
88			`i1 => p(6),`
89			`i0 => q);`
90			`r_7 : a2_x2`
91			`PORT MAP (`
92			`vss => vss,`
93			`vdd => vdd,`
94			`q => r(7),`
95			`i1 => p(7),`
96			`i0 => q);`
97			`r_8 : a2_x2`
98			`PORT MAP (`
99			`vss => vss,`
100			`vdd => vdd,`
101			`q => r(8),`
102			`i1 => p(8),`
103			`i0 => q);`
104			`r_9 : a2_x2`
105			`PORT MAP (`
106			`vss => vss,`
107			`vdd => vdd,`
108			`q => r(9),`
109			`i1 => p(9),`
110			`i0 => q);`
111			`r_10 : a2_x2`
112			`PORT MAP (`
113			`vss => vss,`
114			`vdd => vdd,`
115			`q => r(10),`
116			`i1 => p(10),`
117			`i0 => q);`
118			`r_11 : a2_x2`
119			`PORT MAP (`
120			`vss => vss,`
121			`vdd => vdd,`
122			`q => r(11),`
123			`i1 => p(11),`
124			`i0 => q);`
125			`r_12 : a2_x2`
126			`PORT MAP (`
127			`vss => vss,`
128			`vdd => vdd,`
129			`q => r(12),`
130			`i1 => p(12),`
131			`i0 => q);`
132			`r_13 : a2_x2`
133			`PORT MAP (`
134			`vss => vss,`
135			`vdd => vdd,`
136			`q => r(13),`
137			`i1 => p(13),`
138			`i0 => q);`
139			`r_14 : a2_x2`
140			`PORT MAP (`
141			`vss => vss,`
142			`vdd => vdd,`
143			`q => r(14),`
144			`i1 => p(14),`
145			`i0 => q);`
146			`r_15 : a2_x2`
147			`PORT MAP (`
148			`vss => vss,`
149			`vdd => vdd,`
150			`q => r(15),`
151			`i1 => p(15),`
152			`i0 => q);`
153			`r_16 : a2_x2`
154			`PORT MAP (`
155			`vss => vss,`
156			`vdd => vdd,`
157			`q => r(16),`
158			`i1 => p(16),`
159			`i0 => q);`
160			`r_17 : zero_x0`
161			`PORT MAP (`
162			`vss => vss,`
163			`vdd => vdd,`
164			`nq => r(17));`
165			`r_18 : zero_x0`
166			`PORT MAP (`
167			`vss => vss,`
168			`vdd => vdd,`
169			`nq => r(18));`
170			`r_19 : zero_x0`
171			`PORT MAP (`
172			`vss => vss,`
173			`vdd => vdd,`
174			`nq => r(19));`
175			`r_20 : zero_x0`
176			`PORT MAP (`
177			`vss => vss,`
178			`vdd => vdd,`
179			`nq => r(20));`
180			`r_21 : zero_x0`
181			`PORT MAP (`
182			`vss => vss,`
183			`vdd => vdd,`
184			`nq => r(21));`
185			`r_22 : zero_x0`
186			`PORT MAP (`
187			`vss => vss,`
188			`vdd => vdd,`
189			`nq => r(22));`
190			`r_23 : zero_x0`
191			`PORT MAP (`
192			`vss => vss,`
193			`vdd => vdd,`
194			`nq => r(23));`
195			`r_24 : zero_x0`
196			`PORT MAP (`
197			`vss => vss,`
198			`vdd => vdd,`
199			`nq => r(24));`
200			`r_25 : zero_x0`
201			`PORT MAP (`
202			`vss => vss,`
203			`vdd => vdd,`
204			`nq => r(25));`
205			`r_26 : zero_x0`
206			`PORT MAP (`
207			`vss => vss,`
208			`vdd => vdd,`
209			`nq => r(26));`
210			`r_27 : zero_x0`
211			`PORT MAP (`
212			`vss => vss,`
213			`vdd => vdd,`
214			`nq => r(27));`
215			`r_28 : zero_x0`
216			`PORT MAP (`
217			`vss => vss,`
218			`vdd => vdd,`
219			`nq => r(28));`
220			`r_29 : zero_x0`
221			`PORT MAP (`
222			`vss => vss,`
223			`vdd => vdd,`
224			`nq => r(29));`
225			`r_30 : zero_x0`
226			`PORT MAP (`
227			`vss => vss,`
228			`vdd => vdd,`
229			`nq => r(30));`
230			`r_31 : zero_x0`
231			`PORT MAP (`
232			`vss => vss,`
233			`vdd => vdd,`
234			`nq => r(31));`
235			`r_32 : zero_x0`
236			`PORT MAP (`
237			`vss => vss,`
238			`vdd => vdd,`
239			`nq => r(32));`
240			`r_33 : zero_x0`
241			`PORT MAP (`
242			`vss => vss,`
243			`vdd => vdd,`
244			`nq => r(33));`
245
246			`end VST;`