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[/] [structural_vhdl/] [tags/] [vlsi/] [key_regulator/] [leftshiftregister4.vst] - Blame information for rev 4

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-- VHDL structural description generated from `leftshiftregister4`
--              date : Tue Jul 31 10:16:40 2001
 
 
-- Entity Declaration
 
ENTITY leftshiftregister4 IS
  PORT (
  p : in BIT_VECTOR (16 DOWNTO 0);      -- p
  q : in BIT;   -- q
  r : out BIT_VECTOR (33 DOWNTO 0);     -- r
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END leftshiftregister4;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF leftshiftregister4 IS
  COMPONENT a2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT zero_x0
    port (
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
 
BEGIN
 
  r_0 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(0));
  r_1 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(1));
  r_2 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(2));
  r_3 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(3));
  r_4 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(4),
    i1 => p(0),
    i0 => q);
  r_5 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(5),
    i1 => p(1),
    i0 => q);
  r_6 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(6),
    i1 => p(2),
    i0 => q);
  r_7 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(7),
    i1 => p(3),
    i0 => q);
  r_8 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(8),
    i1 => p(4),
    i0 => q);
  r_9 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(9),
    i1 => p(5),
    i0 => q);
  r_10 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(10),
    i1 => p(6),
    i0 => q);
  r_11 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(11),
    i1 => p(7),
    i0 => q);
  r_12 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(12),
    i1 => p(8),
    i0 => q);
  r_13 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(13),
    i1 => p(9),
    i0 => q);
  r_14 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(14),
    i1 => p(10),
    i0 => q);
  r_15 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(15),
    i1 => p(11),
    i0 => q);
  r_16 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(16),
    i1 => p(12),
    i0 => q);
  r_17 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(17),
    i1 => p(13),
    i0 => q);
  r_18 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(18),
    i1 => p(14),
    i0 => q);
  r_19 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(19),
    i1 => p(15),
    i0 => q);
  r_20 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => r(20),
    i1 => p(16),
    i0 => q);
  r_21 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(21));
  r_22 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(22));
  r_23 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(23));
  r_24 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(24));
  r_25 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(25));
  r_26 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(26));
  r_27 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(27));
  r_28 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(28));
  r_29 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(29));
  r_30 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(30));
  r_31 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(31));
  r_32 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(32));
  r_33 : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => r(33));
 
end VST;

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Subversion Repositories structural_vhdl

[/] [structural_vhdl/] [tags/] [vlsi/] [key_regulator/] [leftshiftregister4.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `leftshiftregister4`
2			`-- date : Tue Jul 31 10:16:40 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY leftshiftregister4 IS`
8			`PORT (`
9			`p : in BIT_VECTOR (16 DOWNTO 0); -- p`
10			`q : in BIT; -- q`
11			`r : out BIT_VECTOR (33 DOWNTO 0); -- r`
12			`vdd : in BIT; -- vdd`
13			`vss : in BIT -- vss`
14			`);`
15			`END leftshiftregister4;`
16
17			`-- Architecture Declaration`
18
19			`ARCHITECTURE VST OF leftshiftregister4 IS`
20			`COMPONENT a2_x2`
21			`port (`
22			`i0 : in BIT; -- i0`
23			`i1 : in BIT; -- i1`
24			`q : out BIT; -- q`
25			`vdd : in BIT; -- vdd`
26			`vss : in BIT -- vss`
27			`);`
28			`END COMPONENT;`
29
30			`COMPONENT zero_x0`
31			`port (`
32			`nq : out BIT; -- nq`
33			`vdd : in BIT; -- vdd`
34			`vss : in BIT -- vss`
35			`);`
36			`END COMPONENT;`
37
38
39			`BEGIN`
40
41			`r_0 : zero_x0`
42			`PORT MAP (`
43			`vss => vss,`
44			`vdd => vdd,`
45			`nq => r(0));`
46			`r_1 : zero_x0`
47			`PORT MAP (`
48			`vss => vss,`
49			`vdd => vdd,`
50			`nq => r(1));`
51			`r_2 : zero_x0`
52			`PORT MAP (`
53			`vss => vss,`
54			`vdd => vdd,`
55			`nq => r(2));`
56			`r_3 : zero_x0`
57			`PORT MAP (`
58			`vss => vss,`
59			`vdd => vdd,`
60			`nq => r(3));`
61			`r_4 : a2_x2`
62			`PORT MAP (`
63			`vss => vss,`
64			`vdd => vdd,`
65			`q => r(4),`
66			`i1 => p(0),`
67			`i0 => q);`
68			`r_5 : a2_x2`
69			`PORT MAP (`
70			`vss => vss,`
71			`vdd => vdd,`
72			`q => r(5),`
73			`i1 => p(1),`
74			`i0 => q);`
75			`r_6 : a2_x2`
76			`PORT MAP (`
77			`vss => vss,`
78			`vdd => vdd,`
79			`q => r(6),`
80			`i1 => p(2),`
81			`i0 => q);`
82			`r_7 : a2_x2`
83			`PORT MAP (`
84			`vss => vss,`
85			`vdd => vdd,`
86			`q => r(7),`
87			`i1 => p(3),`
88			`i0 => q);`
89			`r_8 : a2_x2`
90			`PORT MAP (`
91			`vss => vss,`
92			`vdd => vdd,`
93			`q => r(8),`
94			`i1 => p(4),`
95			`i0 => q);`
96			`r_9 : a2_x2`
97			`PORT MAP (`
98			`vss => vss,`
99			`vdd => vdd,`
100			`q => r(9),`
101			`i1 => p(5),`
102			`i0 => q);`
103			`r_10 : a2_x2`
104			`PORT MAP (`
105			`vss => vss,`
106			`vdd => vdd,`
107			`q => r(10),`
108			`i1 => p(6),`
109			`i0 => q);`
110			`r_11 : a2_x2`
111			`PORT MAP (`
112			`vss => vss,`
113			`vdd => vdd,`
114			`q => r(11),`
115			`i1 => p(7),`
116			`i0 => q);`
117			`r_12 : a2_x2`
118			`PORT MAP (`
119			`vss => vss,`
120			`vdd => vdd,`
121			`q => r(12),`
122			`i1 => p(8),`
123			`i0 => q);`
124			`r_13 : a2_x2`
125			`PORT MAP (`
126			`vss => vss,`
127			`vdd => vdd,`
128			`q => r(13),`
129			`i1 => p(9),`
130			`i0 => q);`
131			`r_14 : a2_x2`
132			`PORT MAP (`
133			`vss => vss,`
134			`vdd => vdd,`
135			`q => r(14),`
136			`i1 => p(10),`
137			`i0 => q);`
138			`r_15 : a2_x2`
139			`PORT MAP (`
140			`vss => vss,`
141			`vdd => vdd,`
142			`q => r(15),`
143			`i1 => p(11),`
144			`i0 => q);`
145			`r_16 : a2_x2`
146			`PORT MAP (`
147			`vss => vss,`
148			`vdd => vdd,`
149			`q => r(16),`
150			`i1 => p(12),`
151			`i0 => q);`
152			`r_17 : a2_x2`
153			`PORT MAP (`
154			`vss => vss,`
155			`vdd => vdd,`
156			`q => r(17),`
157			`i1 => p(13),`
158			`i0 => q);`
159			`r_18 : a2_x2`
160			`PORT MAP (`
161			`vss => vss,`
162			`vdd => vdd,`
163			`q => r(18),`
164			`i1 => p(14),`
165			`i0 => q);`
166			`r_19 : a2_x2`
167			`PORT MAP (`
168			`vss => vss,`
169			`vdd => vdd,`
170			`q => r(19),`
171			`i1 => p(15),`
172			`i0 => q);`
173			`r_20 : a2_x2`
174			`PORT MAP (`
175			`vss => vss,`
176			`vdd => vdd,`
177			`q => r(20),`
178			`i1 => p(16),`
179			`i0 => q);`
180			`r_21 : zero_x0`
181			`PORT MAP (`
182			`vss => vss,`
183			`vdd => vdd,`
184			`nq => r(21));`
185			`r_22 : zero_x0`
186			`PORT MAP (`
187			`vss => vss,`
188			`vdd => vdd,`
189			`nq => r(22));`
190			`r_23 : zero_x0`
191			`PORT MAP (`
192			`vss => vss,`
193			`vdd => vdd,`
194			`nq => r(23));`
195			`r_24 : zero_x0`
196			`PORT MAP (`
197			`vss => vss,`
198			`vdd => vdd,`
199			`nq => r(24));`
200			`r_25 : zero_x0`
201			`PORT MAP (`
202			`vss => vss,`
203			`vdd => vdd,`
204			`nq => r(25));`
205			`r_26 : zero_x0`
206			`PORT MAP (`
207			`vss => vss,`
208			`vdd => vdd,`
209			`nq => r(26));`
210			`r_27 : zero_x0`
211			`PORT MAP (`
212			`vss => vss,`
213			`vdd => vdd,`
214			`nq => r(27));`
215			`r_28 : zero_x0`
216			`PORT MAP (`
217			`vss => vss,`
218			`vdd => vdd,`
219			`nq => r(28));`
220			`r_29 : zero_x0`
221			`PORT MAP (`
222			`vss => vss,`
223			`vdd => vdd,`
224			`nq => r(29));`
225			`r_30 : zero_x0`
226			`PORT MAP (`
227			`vss => vss,`
228			`vdd => vdd,`
229			`nq => r(30));`
230			`r_31 : zero_x0`
231			`PORT MAP (`
232			`vss => vss,`
233			`vdd => vdd,`
234			`nq => r(31));`
235			`r_32 : zero_x0`
236			`PORT MAP (`
237			`vss => vss,`
238			`vdd => vdd,`
239			`nq => r(32));`
240			`r_33 : zero_x0`
241			`PORT MAP (`
242			`vss => vss,`
243			`vdd => vdd,`
244			`nq => r(33));`
245
246			`end VST;`