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[/] [structural_vhdl/] [tags/] [vlsi/] [key_regulator/] [mux128.vst] - Blame information for rev 4

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-- VHDL structural description generated from `mux128`
--              date : Thu Jul 26 02:14:49 2001
 
 
-- Entity Declaration
 
ENTITY mux128 IS
  PORT (
  a : in BIT_VECTOR (127 DOWNTO 0);     -- a
  b : in BIT_VECTOR (127 DOWNTO 0);     -- b
  sel : in BIT; -- sel
  c : out BIT_VECTOR (127 DOWNTO 0);    -- c
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END mux128;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF mux128 IS
  COMPONENT nao22_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT na2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT inv_x1
    port (
    i : in BIT; -- i
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL auxsc4 : BIT;  -- auxsc4
  SIGNAL auxsc5 : BIT;  -- auxsc5
  SIGNAL auxsc9 : BIT;  -- auxsc9
  SIGNAL auxsc10 : BIT; -- auxsc10
  SIGNAL auxsc14 : BIT; -- auxsc14
  SIGNAL auxsc15 : BIT; -- auxsc15
  SIGNAL auxsc19 : BIT; -- auxsc19
  SIGNAL auxsc20 : BIT; -- auxsc20
  SIGNAL auxsc24 : BIT; -- auxsc24
  SIGNAL auxsc25 : BIT; -- auxsc25
  SIGNAL auxsc29 : BIT; -- auxsc29
  SIGNAL auxsc30 : BIT; -- auxsc30
  SIGNAL auxsc34 : BIT; -- auxsc34
  SIGNAL auxsc35 : BIT; -- auxsc35
  SIGNAL auxsc39 : BIT; -- auxsc39
  SIGNAL auxsc40 : BIT; -- auxsc40
  SIGNAL auxsc44 : BIT; -- auxsc44
  SIGNAL auxsc45 : BIT; -- auxsc45
  SIGNAL auxsc49 : BIT; -- auxsc49
  SIGNAL auxsc50 : BIT; -- auxsc50
  SIGNAL auxsc54 : BIT; -- auxsc54
  SIGNAL auxsc55 : BIT; -- auxsc55
  SIGNAL auxsc59 : BIT; -- auxsc59
  SIGNAL auxsc60 : BIT; -- auxsc60
  SIGNAL auxsc64 : BIT; -- auxsc64
  SIGNAL auxsc65 : BIT; -- auxsc65
  SIGNAL auxsc69 : BIT; -- auxsc69
  SIGNAL auxsc70 : BIT; -- auxsc70
  SIGNAL auxsc74 : BIT; -- auxsc74
  SIGNAL auxsc75 : BIT; -- auxsc75
  SIGNAL auxsc79 : BIT; -- auxsc79
  SIGNAL auxsc80 : BIT; -- auxsc80
  SIGNAL auxsc84 : BIT; -- auxsc84
  SIGNAL auxsc85 : BIT; -- auxsc85
  SIGNAL auxsc89 : BIT; -- auxsc89
  SIGNAL auxsc90 : BIT; -- auxsc90
  SIGNAL auxsc94 : BIT; -- auxsc94
  SIGNAL auxsc95 : BIT; -- auxsc95
  SIGNAL auxsc99 : BIT; -- auxsc99
  SIGNAL auxsc100 : BIT;        -- auxsc100
  SIGNAL auxsc104 : BIT;        -- auxsc104
  SIGNAL auxsc105 : BIT;        -- auxsc105
  SIGNAL auxsc109 : BIT;        -- auxsc109
  SIGNAL auxsc110 : BIT;        -- auxsc110
  SIGNAL auxsc114 : BIT;        -- auxsc114
  SIGNAL auxsc115 : BIT;        -- auxsc115
  SIGNAL auxsc119 : BIT;        -- auxsc119
  SIGNAL auxsc120 : BIT;        -- auxsc120
  SIGNAL auxsc124 : BIT;        -- auxsc124
  SIGNAL auxsc125 : BIT;        -- auxsc125
  SIGNAL auxsc129 : BIT;        -- auxsc129
  SIGNAL auxsc130 : BIT;        -- auxsc130
  SIGNAL auxsc134 : BIT;        -- auxsc134
  SIGNAL auxsc135 : BIT;        -- auxsc135
  SIGNAL auxsc139 : BIT;        -- auxsc139
  SIGNAL auxsc140 : BIT;        -- auxsc140
  SIGNAL auxsc144 : BIT;        -- auxsc144
  SIGNAL auxsc145 : BIT;        -- auxsc145
  SIGNAL auxsc149 : BIT;        -- auxsc149
  SIGNAL auxsc150 : BIT;        -- auxsc150
  SIGNAL auxsc154 : BIT;        -- auxsc154
  SIGNAL auxsc155 : BIT;        -- auxsc155
  SIGNAL auxsc159 : BIT;        -- auxsc159
  SIGNAL auxsc160 : BIT;        -- auxsc160
  SIGNAL auxsc164 : BIT;        -- auxsc164
  SIGNAL auxsc165 : BIT;        -- auxsc165
  SIGNAL auxsc169 : BIT;        -- auxsc169
  SIGNAL auxsc170 : BIT;        -- auxsc170
  SIGNAL auxsc174 : BIT;        -- auxsc174
  SIGNAL auxsc175 : BIT;        -- auxsc175
  SIGNAL auxsc179 : BIT;        -- auxsc179
  SIGNAL auxsc180 : BIT;        -- auxsc180
  SIGNAL auxsc184 : BIT;        -- auxsc184
  SIGNAL auxsc185 : BIT;        -- auxsc185
  SIGNAL auxsc189 : BIT;        -- auxsc189
  SIGNAL auxsc190 : BIT;        -- auxsc190
  SIGNAL auxsc194 : BIT;        -- auxsc194
  SIGNAL auxsc195 : BIT;        -- auxsc195
  SIGNAL auxsc199 : BIT;        -- auxsc199
  SIGNAL auxsc200 : BIT;        -- auxsc200
  SIGNAL auxsc204 : BIT;        -- auxsc204
  SIGNAL auxsc205 : BIT;        -- auxsc205
  SIGNAL auxsc209 : BIT;        -- auxsc209
  SIGNAL auxsc210 : BIT;        -- auxsc210
  SIGNAL auxsc214 : BIT;        -- auxsc214
  SIGNAL auxsc215 : BIT;        -- auxsc215
  SIGNAL auxsc219 : BIT;        -- auxsc219
  SIGNAL auxsc220 : BIT;        -- auxsc220
  SIGNAL auxsc224 : BIT;        -- auxsc224
  SIGNAL auxsc225 : BIT;        -- auxsc225
  SIGNAL auxsc229 : BIT;        -- auxsc229
  SIGNAL auxsc230 : BIT;        -- auxsc230
  SIGNAL auxsc234 : BIT;        -- auxsc234
  SIGNAL auxsc235 : BIT;        -- auxsc235
  SIGNAL auxsc239 : BIT;        -- auxsc239
  SIGNAL auxsc240 : BIT;        -- auxsc240
  SIGNAL auxsc244 : BIT;        -- auxsc244
  SIGNAL auxsc245 : BIT;        -- auxsc245
  SIGNAL auxsc249 : BIT;        -- auxsc249
  SIGNAL auxsc250 : BIT;        -- auxsc250
  SIGNAL auxsc254 : BIT;        -- auxsc254
  SIGNAL auxsc255 : BIT;        -- auxsc255
  SIGNAL auxsc259 : BIT;        -- auxsc259
  SIGNAL auxsc260 : BIT;        -- auxsc260
  SIGNAL auxsc264 : BIT;        -- auxsc264
  SIGNAL auxsc265 : BIT;        -- auxsc265
  SIGNAL auxsc269 : BIT;        -- auxsc269
  SIGNAL auxsc270 : BIT;        -- auxsc270
  SIGNAL auxsc274 : BIT;        -- auxsc274
  SIGNAL auxsc275 : BIT;        -- auxsc275
  SIGNAL auxsc279 : BIT;        -- auxsc279
  SIGNAL auxsc280 : BIT;        -- auxsc280
  SIGNAL auxsc284 : BIT;        -- auxsc284
  SIGNAL auxsc285 : BIT;        -- auxsc285
  SIGNAL auxsc289 : BIT;        -- auxsc289
  SIGNAL auxsc290 : BIT;        -- auxsc290
  SIGNAL auxsc294 : BIT;        -- auxsc294
  SIGNAL auxsc295 : BIT;        -- auxsc295
  SIGNAL auxsc299 : BIT;        -- auxsc299
  SIGNAL auxsc300 : BIT;        -- auxsc300
  SIGNAL auxsc304 : BIT;        -- auxsc304
  SIGNAL auxsc305 : BIT;        -- auxsc305
  SIGNAL auxsc309 : BIT;        -- auxsc309
  SIGNAL auxsc310 : BIT;        -- auxsc310
  SIGNAL auxsc314 : BIT;        -- auxsc314
  SIGNAL auxsc315 : BIT;        -- auxsc315
  SIGNAL auxsc319 : BIT;        -- auxsc319
  SIGNAL auxsc320 : BIT;        -- auxsc320
  SIGNAL auxsc324 : BIT;        -- auxsc324
  SIGNAL auxsc325 : BIT;        -- auxsc325
  SIGNAL auxsc329 : BIT;        -- auxsc329
  SIGNAL auxsc330 : BIT;        -- auxsc330
  SIGNAL auxsc334 : BIT;        -- auxsc334
  SIGNAL auxsc335 : BIT;        -- auxsc335
  SIGNAL auxsc339 : BIT;        -- auxsc339
  SIGNAL auxsc340 : BIT;        -- auxsc340
  SIGNAL auxsc344 : BIT;        -- auxsc344
  SIGNAL auxsc345 : BIT;        -- auxsc345
  SIGNAL auxsc349 : BIT;        -- auxsc349
  SIGNAL auxsc350 : BIT;        -- auxsc350
  SIGNAL auxsc354 : BIT;        -- auxsc354
  SIGNAL auxsc355 : BIT;        -- auxsc355
  SIGNAL auxsc359 : BIT;        -- auxsc359
  SIGNAL auxsc360 : BIT;        -- auxsc360
  SIGNAL auxsc364 : BIT;        -- auxsc364
  SIGNAL auxsc365 : BIT;        -- auxsc365
  SIGNAL auxsc369 : BIT;        -- auxsc369
  SIGNAL auxsc370 : BIT;        -- auxsc370
  SIGNAL auxsc374 : BIT;        -- auxsc374
  SIGNAL auxsc375 : BIT;        -- auxsc375
  SIGNAL auxsc379 : BIT;        -- auxsc379
  SIGNAL auxsc380 : BIT;        -- auxsc380
  SIGNAL auxsc384 : BIT;        -- auxsc384
  SIGNAL auxsc385 : BIT;        -- auxsc385
  SIGNAL auxsc389 : BIT;        -- auxsc389
  SIGNAL auxsc390 : BIT;        -- auxsc390
  SIGNAL auxsc394 : BIT;        -- auxsc394
  SIGNAL auxsc395 : BIT;        -- auxsc395
  SIGNAL auxsc399 : BIT;        -- auxsc399
  SIGNAL auxsc400 : BIT;        -- auxsc400
  SIGNAL auxsc404 : BIT;        -- auxsc404
  SIGNAL auxsc405 : BIT;        -- auxsc405
  SIGNAL auxsc409 : BIT;        -- auxsc409
  SIGNAL auxsc410 : BIT;        -- auxsc410
  SIGNAL auxsc414 : BIT;        -- auxsc414
  SIGNAL auxsc415 : BIT;        -- auxsc415
  SIGNAL auxsc419 : BIT;        -- auxsc419
  SIGNAL auxsc420 : BIT;        -- auxsc420
  SIGNAL auxsc424 : BIT;        -- auxsc424
  SIGNAL auxsc425 : BIT;        -- auxsc425
  SIGNAL auxsc429 : BIT;        -- auxsc429
  SIGNAL auxsc430 : BIT;        -- auxsc430
  SIGNAL auxsc434 : BIT;        -- auxsc434
  SIGNAL auxsc435 : BIT;        -- auxsc435
  SIGNAL auxsc439 : BIT;        -- auxsc439
  SIGNAL auxsc440 : BIT;        -- auxsc440
  SIGNAL auxsc444 : BIT;        -- auxsc444
  SIGNAL auxsc445 : BIT;        -- auxsc445
  SIGNAL auxsc449 : BIT;        -- auxsc449
  SIGNAL auxsc450 : BIT;        -- auxsc450
  SIGNAL auxsc454 : BIT;        -- auxsc454
  SIGNAL auxsc455 : BIT;        -- auxsc455
  SIGNAL auxsc459 : BIT;        -- auxsc459
  SIGNAL auxsc460 : BIT;        -- auxsc460
  SIGNAL auxsc464 : BIT;        -- auxsc464
  SIGNAL auxsc465 : BIT;        -- auxsc465
  SIGNAL auxsc469 : BIT;        -- auxsc469
  SIGNAL auxsc470 : BIT;        -- auxsc470
  SIGNAL auxsc474 : BIT;        -- auxsc474
  SIGNAL auxsc475 : BIT;        -- auxsc475
  SIGNAL auxsc479 : BIT;        -- auxsc479
  SIGNAL auxsc480 : BIT;        -- auxsc480
  SIGNAL auxsc484 : BIT;        -- auxsc484
  SIGNAL auxsc485 : BIT;        -- auxsc485
  SIGNAL auxsc489 : BIT;        -- auxsc489
  SIGNAL auxsc490 : BIT;        -- auxsc490
  SIGNAL auxsc494 : BIT;        -- auxsc494
  SIGNAL auxsc495 : BIT;        -- auxsc495
  SIGNAL auxsc499 : BIT;        -- auxsc499
  SIGNAL auxsc500 : BIT;        -- auxsc500
  SIGNAL auxsc504 : BIT;        -- auxsc504
  SIGNAL auxsc505 : BIT;        -- auxsc505
  SIGNAL auxsc509 : BIT;        -- auxsc509
  SIGNAL auxsc510 : BIT;        -- auxsc510
  SIGNAL auxsc514 : BIT;        -- auxsc514
  SIGNAL auxsc515 : BIT;        -- auxsc515
  SIGNAL auxsc519 : BIT;        -- auxsc519
  SIGNAL auxsc520 : BIT;        -- auxsc520
  SIGNAL auxsc524 : BIT;        -- auxsc524
  SIGNAL auxsc525 : BIT;        -- auxsc525
  SIGNAL auxsc529 : BIT;        -- auxsc529
  SIGNAL auxsc530 : BIT;        -- auxsc530
  SIGNAL auxsc534 : BIT;        -- auxsc534
  SIGNAL auxsc535 : BIT;        -- auxsc535
  SIGNAL auxsc539 : BIT;        -- auxsc539
  SIGNAL auxsc540 : BIT;        -- auxsc540
  SIGNAL auxsc544 : BIT;        -- auxsc544
  SIGNAL auxsc545 : BIT;        -- auxsc545
  SIGNAL auxsc549 : BIT;        -- auxsc549
  SIGNAL auxsc550 : BIT;        -- auxsc550
  SIGNAL auxsc554 : BIT;        -- auxsc554
  SIGNAL auxsc555 : BIT;        -- auxsc555
  SIGNAL auxsc559 : BIT;        -- auxsc559
  SIGNAL auxsc560 : BIT;        -- auxsc560
  SIGNAL auxsc564 : BIT;        -- auxsc564
  SIGNAL auxsc565 : BIT;        -- auxsc565
  SIGNAL auxsc569 : BIT;        -- auxsc569
  SIGNAL auxsc570 : BIT;        -- auxsc570
  SIGNAL auxsc574 : BIT;        -- auxsc574
  SIGNAL auxsc575 : BIT;        -- auxsc575
  SIGNAL auxsc579 : BIT;        -- auxsc579
  SIGNAL auxsc580 : BIT;        -- auxsc580
  SIGNAL auxsc584 : BIT;        -- auxsc584
  SIGNAL auxsc585 : BIT;        -- auxsc585
  SIGNAL auxsc589 : BIT;        -- auxsc589
  SIGNAL auxsc590 : BIT;        -- auxsc590
  SIGNAL auxsc594 : BIT;        -- auxsc594
  SIGNAL auxsc595 : BIT;        -- auxsc595
  SIGNAL auxsc599 : BIT;        -- auxsc599
  SIGNAL auxsc600 : BIT;        -- auxsc600
  SIGNAL auxsc604 : BIT;        -- auxsc604
  SIGNAL auxsc605 : BIT;        -- auxsc605
  SIGNAL auxsc609 : BIT;        -- auxsc609
  SIGNAL auxsc610 : BIT;        -- auxsc610
  SIGNAL auxsc614 : BIT;        -- auxsc614
  SIGNAL auxsc615 : BIT;        -- auxsc615
  SIGNAL auxsc619 : BIT;        -- auxsc619
  SIGNAL auxsc620 : BIT;        -- auxsc620
  SIGNAL auxsc624 : BIT;        -- auxsc624
  SIGNAL auxsc625 : BIT;        -- auxsc625
  SIGNAL auxsc629 : BIT;        -- auxsc629
  SIGNAL auxsc630 : BIT;        -- auxsc630
  SIGNAL auxsc634 : BIT;        -- auxsc634
  SIGNAL auxsc635 : BIT;        -- auxsc635
  SIGNAL auxsc639 : BIT;        -- auxsc639
  SIGNAL auxsc640 : BIT;        -- auxsc640
 
BEGIN
 
  c_0 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(0),
    i2 => auxsc5,
    i1 => auxsc4,
    i0 => sel);
  c_1 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(1),
    i2 => auxsc10,
    i1 => auxsc9,
    i0 => sel);
  c_2 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(2),
    i2 => auxsc15,
    i1 => auxsc14,
    i0 => sel);
  c_3 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(3),
    i2 => auxsc20,
    i1 => auxsc19,
    i0 => sel);
  c_4 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(4),
    i2 => auxsc25,
    i1 => auxsc24,
    i0 => sel);
  c_5 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(5),
    i2 => auxsc30,
    i1 => auxsc29,
    i0 => sel);
  c_6 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(6),
    i2 => auxsc35,
    i1 => auxsc34,
    i0 => sel);
  c_7 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(7),
    i2 => auxsc40,
    i1 => auxsc39,
    i0 => sel);
  c_8 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(8),
    i2 => auxsc45,
    i1 => auxsc44,
    i0 => sel);
  c_9 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(9),
    i2 => auxsc50,
    i1 => auxsc49,
    i0 => sel);
  c_10 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(10),
    i2 => auxsc55,
    i1 => auxsc54,
    i0 => sel);
  c_11 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(11),
    i2 => auxsc60,
    i1 => auxsc59,
    i0 => sel);
  c_12 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(12),
    i2 => auxsc65,
    i1 => auxsc64,
    i0 => sel);
  c_13 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(13),
    i2 => auxsc70,
    i1 => auxsc69,
    i0 => sel);
  c_14 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(14),
    i2 => auxsc75,
    i1 => auxsc74,
    i0 => sel);
  c_15 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(15),
    i2 => auxsc80,
    i1 => auxsc79,
    i0 => sel);
  c_16 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(16),
    i2 => auxsc85,
    i1 => auxsc84,
    i0 => sel);
  c_17 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(17),
    i2 => auxsc90,
    i1 => auxsc89,
    i0 => sel);
  c_18 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(18),
    i2 => auxsc95,
    i1 => auxsc94,
    i0 => sel);
  c_19 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(19),
    i2 => auxsc100,
    i1 => auxsc99,
    i0 => sel);
  c_20 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(20),
    i2 => auxsc105,
    i1 => auxsc104,
    i0 => sel);
  c_21 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(21),
    i2 => auxsc110,
    i1 => auxsc109,
    i0 => sel);
  c_22 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(22),
    i2 => auxsc115,
    i1 => auxsc114,
    i0 => sel);
  c_23 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(23),
    i2 => auxsc120,
    i1 => auxsc119,
    i0 => sel);
  c_24 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(24),
    i2 => auxsc125,
    i1 => auxsc124,
    i0 => sel);
  c_25 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(25),
    i2 => auxsc130,
    i1 => auxsc129,
    i0 => sel);
  c_26 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(26),
    i2 => auxsc135,
    i1 => auxsc134,
    i0 => sel);
  c_27 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(27),
    i2 => auxsc140,
    i1 => auxsc139,
    i0 => sel);
  c_28 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(28),
    i2 => auxsc145,
    i1 => auxsc144,
    i0 => sel);
  c_29 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(29),
    i2 => auxsc150,
    i1 => auxsc149,
    i0 => sel);
  c_30 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(30),
    i2 => auxsc155,
    i1 => auxsc154,
    i0 => sel);
  c_31 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(31),
    i2 => auxsc160,
    i1 => auxsc159,
    i0 => sel);
  c_32 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(32),
    i2 => auxsc165,
    i1 => auxsc164,
    i0 => sel);
  c_33 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(33),
    i2 => auxsc170,
    i1 => auxsc169,
    i0 => sel);
  c_34 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(34),
    i2 => auxsc175,
    i1 => auxsc174,
    i0 => sel);
  c_35 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(35),
    i2 => auxsc180,
    i1 => auxsc179,
    i0 => sel);
  c_36 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(36),
    i2 => auxsc185,
    i1 => auxsc184,
    i0 => sel);
  c_37 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(37),
    i2 => auxsc190,
    i1 => auxsc189,
    i0 => sel);
  c_38 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(38),
    i2 => auxsc195,
    i1 => auxsc194,
    i0 => sel);
  c_39 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(39),
    i2 => auxsc200,
    i1 => auxsc199,
    i0 => sel);
  c_40 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(40),
    i2 => auxsc205,
    i1 => auxsc204,
    i0 => sel);
  c_41 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(41),
    i2 => auxsc210,
    i1 => auxsc209,
    i0 => sel);
  c_42 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(42),
    i2 => auxsc215,
    i1 => auxsc214,
    i0 => sel);
  c_43 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(43),
    i2 => auxsc220,
    i1 => auxsc219,
    i0 => sel);
  c_44 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(44),
    i2 => auxsc225,
    i1 => auxsc224,
    i0 => sel);
  c_45 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(45),
    i2 => auxsc230,
    i1 => auxsc229,
    i0 => sel);
  c_46 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(46),
    i2 => auxsc235,
    i1 => auxsc234,
    i0 => sel);
  c_47 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(47),
    i2 => auxsc240,
    i1 => auxsc239,
    i0 => sel);
  c_48 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(48),
    i2 => auxsc245,
    i1 => auxsc244,
    i0 => sel);
  c_49 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(49),
    i2 => auxsc250,
    i1 => auxsc249,
    i0 => sel);
  c_50 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(50),
    i2 => auxsc255,
    i1 => auxsc254,
    i0 => sel);
  c_51 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(51),
    i2 => auxsc260,
    i1 => auxsc259,
    i0 => sel);
  c_52 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(52),
    i2 => auxsc265,
    i1 => auxsc264,
    i0 => sel);
  c_53 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(53),
    i2 => auxsc270,
    i1 => auxsc269,
    i0 => sel);
  c_54 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(54),
    i2 => auxsc275,
    i1 => auxsc274,
    i0 => sel);
  c_55 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(55),
    i2 => auxsc280,
    i1 => auxsc279,
    i0 => sel);
  c_56 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(56),
    i2 => auxsc285,
    i1 => auxsc284,
    i0 => sel);
  c_57 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(57),
    i2 => auxsc290,
    i1 => auxsc289,
    i0 => sel);
  c_58 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(58),
    i2 => auxsc295,
    i1 => auxsc294,
    i0 => sel);
  c_59 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(59),
    i2 => auxsc300,
    i1 => auxsc299,
    i0 => sel);
  c_60 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(60),
    i2 => auxsc305,
    i1 => auxsc304,
    i0 => sel);
  c_61 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(61),
    i2 => auxsc310,
    i1 => auxsc309,
    i0 => sel);
  c_62 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(62),
    i2 => auxsc315,
    i1 => auxsc314,
    i0 => sel);
  c_63 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(63),
    i2 => auxsc320,
    i1 => auxsc319,
    i0 => sel);
  c_64 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(64),
    i2 => auxsc325,
    i1 => auxsc324,
    i0 => sel);
  c_65 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(65),
    i2 => auxsc330,
    i1 => auxsc329,
    i0 => sel);
  c_66 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(66),
    i2 => auxsc335,
    i1 => auxsc334,
    i0 => sel);
  c_67 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(67),
    i2 => auxsc340,
    i1 => auxsc339,
    i0 => sel);
  c_68 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(68),
    i2 => auxsc345,
    i1 => auxsc344,
    i0 => sel);
  c_69 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(69),
    i2 => auxsc350,
    i1 => auxsc349,
    i0 => sel);
  c_70 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(70),
    i2 => auxsc355,
    i1 => auxsc354,
    i0 => sel);
  c_71 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(71),
    i2 => auxsc360,
    i1 => auxsc359,
    i0 => sel);
  c_72 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(72),
    i2 => auxsc365,
    i1 => auxsc364,
    i0 => sel);
  c_73 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(73),
    i2 => auxsc370,
    i1 => auxsc369,
    i0 => sel);
  c_74 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(74),
    i2 => auxsc375,
    i1 => auxsc374,
    i0 => sel);
  c_75 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(75),
    i2 => auxsc380,
    i1 => auxsc379,
    i0 => sel);
  c_76 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(76),
    i2 => auxsc385,
    i1 => auxsc384,
    i0 => sel);
  c_77 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(77),
    i2 => auxsc390,
    i1 => auxsc389,
    i0 => sel);
  c_78 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(78),
    i2 => auxsc395,
    i1 => auxsc394,
    i0 => sel);
  c_79 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(79),
    i2 => auxsc400,
    i1 => auxsc399,
    i0 => sel);
  c_80 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(80),
    i2 => auxsc405,
    i1 => auxsc404,
    i0 => sel);
  c_81 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(81),
    i2 => auxsc410,
    i1 => auxsc409,
    i0 => sel);
  c_82 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(82),
    i2 => auxsc415,
    i1 => auxsc414,
    i0 => sel);
  c_83 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(83),
    i2 => auxsc420,
    i1 => auxsc419,
    i0 => sel);
  c_84 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(84),
    i2 => auxsc425,
    i1 => auxsc424,
    i0 => sel);
  c_85 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(85),
    i2 => auxsc430,
    i1 => auxsc429,
    i0 => sel);
  c_86 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(86),
    i2 => auxsc435,
    i1 => auxsc434,
    i0 => sel);
  c_87 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(87),
    i2 => auxsc440,
    i1 => auxsc439,
    i0 => sel);
  c_88 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(88),
    i2 => auxsc445,
    i1 => auxsc444,
    i0 => sel);
  c_89 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(89),
    i2 => auxsc450,
    i1 => auxsc449,
    i0 => sel);
  c_90 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(90),
    i2 => auxsc455,
    i1 => auxsc454,
    i0 => sel);
  c_91 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(91),
    i2 => auxsc460,
    i1 => auxsc459,
    i0 => sel);
  c_92 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(92),
    i2 => auxsc465,
    i1 => auxsc464,
    i0 => sel);
  c_93 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(93),
    i2 => auxsc470,
    i1 => auxsc469,
    i0 => sel);
  c_94 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(94),
    i2 => auxsc475,
    i1 => auxsc474,
    i0 => sel);
  c_95 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(95),
    i2 => auxsc480,
    i1 => auxsc479,
    i0 => sel);
  c_96 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(96),
    i2 => auxsc485,
    i1 => auxsc484,
    i0 => sel);
  c_97 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(97),
    i2 => auxsc490,
    i1 => auxsc489,
    i0 => sel);
  c_98 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(98),
    i2 => auxsc495,
    i1 => auxsc494,
    i0 => sel);
  c_99 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(99),
    i2 => auxsc500,
    i1 => auxsc499,
    i0 => sel);
  c_100 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(100),
    i2 => auxsc505,
    i1 => auxsc504,
    i0 => sel);
  c_101 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(101),
    i2 => auxsc510,
    i1 => auxsc509,
    i0 => sel);
  c_102 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(102),
    i2 => auxsc515,
    i1 => auxsc514,
    i0 => sel);
  c_103 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(103),
    i2 => auxsc520,
    i1 => auxsc519,
    i0 => sel);
  c_104 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(104),
    i2 => auxsc525,
    i1 => auxsc524,
    i0 => sel);
  c_105 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(105),
    i2 => auxsc530,
    i1 => auxsc529,
    i0 => sel);
  c_106 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(106),
    i2 => auxsc535,
    i1 => auxsc534,
    i0 => sel);
  c_107 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(107),
    i2 => auxsc540,
    i1 => auxsc539,
    i0 => sel);
  c_108 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(108),
    i2 => auxsc545,
    i1 => auxsc544,
    i0 => sel);
  c_109 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(109),
    i2 => auxsc550,
    i1 => auxsc549,
    i0 => sel);
  c_110 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(110),
    i2 => auxsc555,
    i1 => auxsc554,
    i0 => sel);
  c_111 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(111),
    i2 => auxsc560,
    i1 => auxsc559,
    i0 => sel);
  c_112 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(112),
    i2 => auxsc565,
    i1 => auxsc564,
    i0 => sel);
  c_113 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(113),
    i2 => auxsc570,
    i1 => auxsc569,
    i0 => sel);
  c_114 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(114),
    i2 => auxsc575,
    i1 => auxsc574,
    i0 => sel);
  c_115 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(115),
    i2 => auxsc580,
    i1 => auxsc579,
    i0 => sel);
  c_116 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(116),
    i2 => auxsc585,
    i1 => auxsc584,
    i0 => sel);
  c_117 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(117),
    i2 => auxsc590,
    i1 => auxsc589,
    i0 => sel);
  c_118 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(118),
    i2 => auxsc595,
    i1 => auxsc594,
    i0 => sel);
  c_119 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(119),
    i2 => auxsc600,
    i1 => auxsc599,
    i0 => sel);
  c_120 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(120),
    i2 => auxsc605,
    i1 => auxsc604,
    i0 => sel);
  c_121 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(121),
    i2 => auxsc610,
    i1 => auxsc609,
    i0 => sel);
  c_122 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(122),
    i2 => auxsc615,
    i1 => auxsc614,
    i0 => sel);
  c_123 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(123),
    i2 => auxsc620,
    i1 => auxsc619,
    i0 => sel);
  c_124 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(124),
    i2 => auxsc625,
    i1 => auxsc624,
    i0 => sel);
  c_125 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(125),
    i2 => auxsc630,
    i1 => auxsc629,
    i0 => sel);
  c_126 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(126),
    i2 => auxsc635,
    i1 => auxsc634,
    i0 => sel);
  c_127 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(127),
    i2 => auxsc640,
    i1 => auxsc639,
    i0 => sel);
  auxsc640 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc640,
    i1 => b(127),
    i0 => sel);
  auxsc639 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc639,
    i => a(127));
  auxsc635 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc635,
    i1 => b(126),
    i0 => sel);
  auxsc634 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc634,
    i => a(126));
  auxsc630 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc630,
    i1 => b(125),
    i0 => sel);
  auxsc629 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc629,
    i => a(125));
  auxsc625 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc625,
    i1 => b(124),
    i0 => sel);
  auxsc624 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc624,
    i => a(124));
  auxsc620 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc620,
    i1 => b(123),
    i0 => sel);
  auxsc619 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc619,
    i => a(123));
  auxsc615 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc615,
    i1 => b(122),
    i0 => sel);
  auxsc614 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc614,
    i => a(122));
  auxsc610 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc610,
    i1 => b(121),
    i0 => sel);
  auxsc609 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc609,
    i => a(121));
  auxsc605 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc605,
    i1 => b(120),
    i0 => sel);
  auxsc604 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc604,
    i => a(120));
  auxsc600 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc600,
    i1 => b(119),
    i0 => sel);
  auxsc599 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc599,
    i => a(119));
  auxsc595 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc595,
    i1 => b(118),
    i0 => sel);
  auxsc594 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc594,
    i => a(118));
  auxsc590 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc590,
    i1 => b(117),
    i0 => sel);
  auxsc589 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc589,
    i => a(117));
  auxsc585 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc585,
    i1 => b(116),
    i0 => sel);
  auxsc584 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc584,
    i => a(116));
  auxsc580 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc580,
    i1 => b(115),
    i0 => sel);
  auxsc579 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc579,
    i => a(115));
  auxsc575 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc575,
    i1 => b(114),
    i0 => sel);
  auxsc574 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc574,
    i => a(114));
  auxsc570 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc570,
    i1 => b(113),
    i0 => sel);
  auxsc569 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc569,
    i => a(113));
  auxsc565 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc565,
    i1 => b(112),
    i0 => sel);
  auxsc564 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc564,
    i => a(112));
  auxsc560 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc560,
    i1 => b(111),
    i0 => sel);
  auxsc559 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc559,
    i => a(111));
  auxsc555 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc555,
    i1 => b(110),
    i0 => sel);
  auxsc554 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc554,
    i => a(110));
  auxsc550 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc550,
    i1 => b(109),
    i0 => sel);
  auxsc549 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc549,
    i => a(109));
  auxsc545 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc545,
    i1 => b(108),
    i0 => sel);
  auxsc544 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc544,
    i => a(108));
  auxsc540 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc540,
    i1 => b(107),
    i0 => sel);
  auxsc539 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc539,
    i => a(107));
  auxsc535 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc535,
    i1 => b(106),
    i0 => sel);
  auxsc534 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc534,
    i => a(106));
  auxsc530 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc530,
    i1 => b(105),
    i0 => sel);
  auxsc529 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc529,
    i => a(105));
  auxsc525 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc525,
    i1 => b(104),
    i0 => sel);
  auxsc524 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc524,
    i => a(104));
  auxsc520 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc520,
    i1 => b(103),
    i0 => sel);
  auxsc519 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc519,
    i => a(103));
  auxsc515 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc515,
    i1 => b(102),
    i0 => sel);
  auxsc514 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc514,
    i => a(102));
  auxsc510 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc510,
    i1 => b(101),
    i0 => sel);
  auxsc509 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc509,
    i => a(101));
  auxsc505 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc505,
    i1 => b(100),
    i0 => sel);
  auxsc504 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc504,
    i => a(100));
  auxsc500 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc500,
    i1 => b(99),
    i0 => sel);
  auxsc499 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc499,
    i => a(99));
  auxsc495 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc495,
    i1 => b(98),
    i0 => sel);
  auxsc494 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc494,
    i => a(98));
  auxsc490 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc490,
    i1 => b(97),
    i0 => sel);
  auxsc489 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc489,
    i => a(97));
  auxsc485 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc485,
    i1 => b(96),
    i0 => sel);
  auxsc484 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc484,
    i => a(96));
  auxsc480 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc480,
    i1 => b(95),
    i0 => sel);
  auxsc479 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc479,
    i => a(95));
  auxsc475 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc475,
    i1 => b(94),
    i0 => sel);
  auxsc474 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc474,
    i => a(94));
  auxsc470 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc470,
    i1 => b(93),
    i0 => sel);
  auxsc469 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc469,
    i => a(93));
  auxsc465 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc465,
    i1 => b(92),
    i0 => sel);
  auxsc464 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc464,
    i => a(92));
  auxsc460 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc460,
    i1 => b(91),
    i0 => sel);
  auxsc459 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc459,
    i => a(91));
  auxsc455 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc455,
    i1 => b(90),
    i0 => sel);
  auxsc454 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc454,
    i => a(90));
  auxsc450 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc450,
    i1 => b(89),
    i0 => sel);
  auxsc449 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc449,
    i => a(89));
  auxsc445 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc445,
    i1 => b(88),
    i0 => sel);
  auxsc444 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc444,
    i => a(88));
  auxsc440 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc440,
    i1 => b(87),
    i0 => sel);
  auxsc439 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc439,
    i => a(87));
  auxsc435 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc435,
    i1 => b(86),
    i0 => sel);
  auxsc434 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc434,
    i => a(86));
  auxsc430 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc430,
    i1 => b(85),
    i0 => sel);
  auxsc429 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc429,
    i => a(85));
  auxsc425 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc425,
    i1 => b(84),
    i0 => sel);
  auxsc424 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc424,
    i => a(84));
  auxsc420 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc420,
    i1 => b(83),
    i0 => sel);
  auxsc419 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc419,
    i => a(83));
  auxsc415 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc415,
    i1 => b(82),
    i0 => sel);
  auxsc414 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc414,
    i => a(82));
  auxsc410 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc410,
    i1 => b(81),
    i0 => sel);
  auxsc409 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc409,
    i => a(81));
  auxsc405 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc405,
    i1 => b(80),
    i0 => sel);
  auxsc404 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc404,
    i => a(80));
  auxsc400 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc400,
    i1 => b(79),
    i0 => sel);
  auxsc399 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc399,
    i => a(79));
  auxsc395 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc395,
    i1 => b(78),
    i0 => sel);
  auxsc394 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc394,
    i => a(78));
  auxsc390 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc390,
    i1 => b(77),
    i0 => sel);
  auxsc389 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc389,
    i => a(77));
  auxsc385 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc385,
    i1 => b(76),
    i0 => sel);
  auxsc384 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc384,
    i => a(76));
  auxsc380 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc380,
    i1 => b(75),
    i0 => sel);
  auxsc379 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc379,
    i => a(75));
  auxsc375 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc375,
    i1 => b(74),
    i0 => sel);
  auxsc374 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc374,
    i => a(74));
  auxsc370 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc370,
    i1 => b(73),
    i0 => sel);
  auxsc369 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc369,
    i => a(73));
  auxsc365 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc365,
    i1 => b(72),
    i0 => sel);
  auxsc364 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc364,
    i => a(72));
  auxsc360 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc360,
    i1 => b(71),
    i0 => sel);
  auxsc359 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc359,
    i => a(71));
  auxsc355 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc355,
    i1 => b(70),
    i0 => sel);
  auxsc354 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc354,
    i => a(70));
  auxsc350 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc350,
    i1 => b(69),
    i0 => sel);
  auxsc349 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc349,
    i => a(69));
  auxsc345 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc345,
    i1 => b(68),
    i0 => sel);
  auxsc344 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc344,
    i => a(68));
  auxsc340 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc340,
    i1 => b(67),
    i0 => sel);
  auxsc339 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc339,
    i => a(67));
  auxsc335 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc335,
    i1 => b(66),
    i0 => sel);
  auxsc334 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc334,
    i => a(66));
  auxsc330 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc330,
    i1 => b(65),
    i0 => sel);
  auxsc329 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc329,
    i => a(65));
  auxsc325 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc325,
    i1 => b(64),
    i0 => sel);
  auxsc324 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc324,
    i => a(64));
  auxsc320 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc320,
    i1 => b(63),
    i0 => sel);
  auxsc319 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc319,
    i => a(63));
  auxsc315 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc315,
    i1 => b(62),
    i0 => sel);
  auxsc314 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc314,
    i => a(62));
  auxsc310 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc310,
    i1 => b(61),
    i0 => sel);
  auxsc309 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc309,
    i => a(61));
  auxsc305 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc305,
    i1 => b(60),
    i0 => sel);
  auxsc304 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc304,
    i => a(60));
  auxsc300 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc300,
    i1 => b(59),
    i0 => sel);
  auxsc299 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc299,
    i => a(59));
  auxsc295 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc295,
    i1 => b(58),
    i0 => sel);
  auxsc294 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc294,
    i => a(58));
  auxsc290 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc290,
    i1 => b(57),
    i0 => sel);
  auxsc289 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc289,
    i => a(57));
  auxsc285 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc285,
    i1 => b(56),
    i0 => sel);
  auxsc284 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc284,
    i => a(56));
  auxsc280 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc280,
    i1 => b(55),
    i0 => sel);
  auxsc279 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc279,
    i => a(55));
  auxsc275 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc275,
    i1 => b(54),
    i0 => sel);
  auxsc274 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc274,
    i => a(54));
  auxsc270 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc270,
    i1 => b(53),
    i0 => sel);
  auxsc269 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc269,
    i => a(53));
  auxsc265 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc265,
    i1 => b(52),
    i0 => sel);
  auxsc264 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc264,
    i => a(52));
  auxsc260 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc260,
    i1 => b(51),
    i0 => sel);
  auxsc259 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc259,
    i => a(51));
  auxsc255 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc255,
    i1 => b(50),
    i0 => sel);
  auxsc254 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc254,
    i => a(50));
  auxsc250 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc250,
    i1 => b(49),
    i0 => sel);
  auxsc249 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc249,
    i => a(49));
  auxsc245 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc245,
    i1 => b(48),
    i0 => sel);
  auxsc244 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc244,
    i => a(48));
  auxsc240 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc240,
    i1 => b(47),
    i0 => sel);
  auxsc239 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc239,
    i => a(47));
  auxsc235 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc235,
    i1 => b(46),
    i0 => sel);
  auxsc234 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc234,
    i => a(46));
  auxsc230 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc230,
    i1 => b(45),
    i0 => sel);
  auxsc229 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc229,
    i => a(45));
  auxsc225 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc225,
    i1 => b(44),
    i0 => sel);
  auxsc224 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc224,
    i => a(44));
  auxsc220 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc220,
    i1 => b(43),
    i0 => sel);
  auxsc219 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc219,
    i => a(43));
  auxsc215 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc215,
    i1 => b(42),
    i0 => sel);
  auxsc214 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc214,
    i => a(42));
  auxsc210 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc210,
    i1 => b(41),
    i0 => sel);
  auxsc209 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc209,
    i => a(41));
  auxsc205 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc205,
    i1 => b(40),
    i0 => sel);
  auxsc204 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc204,
    i => a(40));
  auxsc200 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc200,
    i1 => b(39),
    i0 => sel);
  auxsc199 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc199,
    i => a(39));
  auxsc195 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc195,
    i1 => b(38),
    i0 => sel);
  auxsc194 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc194,
    i => a(38));
  auxsc190 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc190,
    i1 => b(37),
    i0 => sel);
  auxsc189 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc189,
    i => a(37));
  auxsc185 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc185,
    i1 => b(36),
    i0 => sel);
  auxsc184 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc184,
    i => a(36));
  auxsc180 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc180,
    i1 => b(35),
    i0 => sel);
  auxsc179 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc179,
    i => a(35));
  auxsc175 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc175,
    i1 => b(34),
    i0 => sel);
  auxsc174 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc174,
    i => a(34));
  auxsc170 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc170,
    i1 => b(33),
    i0 => sel);
  auxsc169 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc169,
    i => a(33));
  auxsc165 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc165,
    i1 => b(32),
    i0 => sel);
  auxsc164 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc164,
    i => a(32));
  auxsc160 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc160,
    i1 => b(31),
    i0 => sel);
  auxsc159 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc159,
    i => a(31));
  auxsc155 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc155,
    i1 => b(30),
    i0 => sel);
  auxsc154 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc154,
    i => a(30));
  auxsc150 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc150,
    i1 => b(29),
    i0 => sel);
  auxsc149 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc149,
    i => a(29));
  auxsc145 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc145,
    i1 => b(28),
    i0 => sel);
  auxsc144 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc144,
    i => a(28));
  auxsc140 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc140,
    i1 => b(27),
    i0 => sel);
  auxsc139 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc139,
    i => a(27));
  auxsc135 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc135,
    i1 => b(26),
    i0 => sel);
  auxsc134 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc134,
    i => a(26));
  auxsc130 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc130,
    i1 => b(25),
    i0 => sel);
  auxsc129 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc129,
    i => a(25));
  auxsc125 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc125,
    i1 => b(24),
    i0 => sel);
  auxsc124 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc124,
    i => a(24));
  auxsc120 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc120,
    i1 => b(23),
    i0 => sel);
  auxsc119 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc119,
    i => a(23));
  auxsc115 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc115,
    i1 => b(22),
    i0 => sel);
  auxsc114 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc114,
    i => a(22));
  auxsc110 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc110,
    i1 => b(21),
    i0 => sel);
  auxsc109 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc109,
    i => a(21));
  auxsc105 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc105,
    i1 => b(20),
    i0 => sel);
  auxsc104 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc104,
    i => a(20));
  auxsc100 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc100,
    i1 => b(19),
    i0 => sel);
  auxsc99 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc99,
    i => a(19));
  auxsc95 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc95,
    i1 => b(18),
    i0 => sel);
  auxsc94 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc94,
    i => a(18));
  auxsc90 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc90,
    i1 => b(17),
    i0 => sel);
  auxsc89 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc89,
    i => a(17));
  auxsc85 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc85,
    i1 => b(16),
    i0 => sel);
  auxsc84 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc84,
    i => a(16));
  auxsc80 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc80,
    i1 => b(15),
    i0 => sel);
  auxsc79 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc79,
    i => a(15));
  auxsc75 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc75,
    i1 => b(14),
    i0 => sel);
  auxsc74 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc74,
    i => a(14));
  auxsc70 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc70,
    i1 => b(13),
    i0 => sel);
  auxsc69 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc69,
    i => a(13));
  auxsc65 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc65,
    i1 => b(12),
    i0 => sel);
  auxsc64 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc64,
    i => a(12));
  auxsc60 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc60,
    i1 => b(11),
    i0 => sel);
  auxsc59 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc59,
    i => a(11));
  auxsc55 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc55,
    i1 => b(10),
    i0 => sel);
  auxsc54 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc54,
    i => a(10));
  auxsc50 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc50,
    i1 => b(9),
    i0 => sel);
  auxsc49 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc49,
    i => a(9));
  auxsc45 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc45,
    i1 => b(8),
    i0 => sel);
  auxsc44 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc44,
    i => a(8));
  auxsc40 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc40,
    i1 => b(7),
    i0 => sel);
  auxsc39 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc39,
    i => a(7));
  auxsc35 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc35,
    i1 => b(6),
    i0 => sel);
  auxsc34 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc34,
    i => a(6));
  auxsc30 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc30,
    i1 => b(5),
    i0 => sel);
  auxsc29 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc29,
    i => a(5));
  auxsc25 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc25,
    i1 => b(4),
    i0 => sel);
  auxsc24 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc24,
    i => a(4));
  auxsc20 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc20,
    i1 => b(3),
    i0 => sel);
  auxsc19 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc19,
    i => a(3));
  auxsc15 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc15,
    i1 => b(2),
    i0 => sel);
  auxsc14 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc14,
    i => a(2));
  auxsc10 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc10,
    i1 => b(1),
    i0 => sel);
  auxsc9 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc9,
    i => a(1));
  auxsc5 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc5,
    i1 => b(0),
    i0 => sel);
  auxsc4 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc4,
    i => a(0));
 
end VST;
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[/] [structural_vhdl/] [tags/] [vlsi/] [key_regulator/] [mux128.vst] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `mux128`
2			`-- date : Thu Jul 26 02:14:49 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY mux128 IS`
8			`PORT (`
9			`a : in BIT_VECTOR (127 DOWNTO 0); -- a`
10			`b : in BIT_VECTOR (127 DOWNTO 0); -- b`
11			`sel : in BIT; -- sel`
12			`c : out BIT_VECTOR (127 DOWNTO 0); -- c`
13			`vdd : in BIT; -- vdd`
14			`vss : in BIT -- vss`
15			`);`
16			`END mux128;`
17
18			`-- Architecture Declaration`
19
20			`ARCHITECTURE VST OF mux128 IS`
21			`COMPONENT nao22_x1`
22			`port (`
23			`i0 : in BIT; -- i0`
24			`i1 : in BIT; -- i1`
25			`i2 : in BIT; -- i2`
26			`nq : out BIT; -- nq`
27			`vdd : in BIT; -- vdd`
28			`vss : in BIT -- vss`
29			`);`
30			`END COMPONENT;`
31
32			`COMPONENT na2_x1`
33			`port (`
34			`i0 : in BIT; -- i0`
35			`i1 : in BIT; -- i1`
36			`nq : out BIT; -- nq`
37			`vdd : in BIT; -- vdd`
38			`vss : in BIT -- vss`
39			`);`
40			`END COMPONENT;`