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[/] [structural_vhdl/] [tags/] [vlsi/] [main control/] [controlmode.vst] - Blame information for rev 5

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-- VHDL structural description generated from `controlmode`
--              date : Sat Sep  1 20:27:01 2001
 
 
-- Entity Declaration
 
ENTITY controlmode IS
  PORT (
  clk : in BIT; -- clk
  start : in BIT;       -- start
  mode : in BIT_VECTOR (0 TO 1);        -- mode
  cke : in BIT; -- cke
  ikey_ready : in BIT;  -- ikey_ready
  key_ready : in BIT;   -- key_ready
  dt_ready : in BIT;    -- dt_ready
  finish : in BIT;      -- finish
  req_cp : in BIT;      -- req_cp
  e : in BIT;   -- e
  first_dt : out BIT;   -- first_dt
  e_mesin : out BIT;    -- e_mesin
  s_mesin : out BIT;    -- s_mesin
  s_gen_key : out BIT;  -- s_gen_key
  emp_buf : out BIT;    -- emp_buf
  cp_ready : out BIT;   -- cp_ready
  cke_b_mode : out BIT; -- cke_b_mode
  en_in : out BIT;      -- en_in
  en_iv : out BIT;      -- en_iv
  en_rcbc : out BIT;    -- en_rcbc
  en_out : out BIT;     -- en_out
  sel1 : out BIT_VECTOR (0 TO 1);       -- sel1
  sel2 : out BIT_VECTOR (0 TO 1);       -- sel2
  sel3 : out BIT_VECTOR (0 TO 1);       -- sel3
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END controlmode;
 
-- Architecture Declaration
 
ARCHITECTURE VST OF controlmode IS
  COMPONENT dec_mode
    port (
    start : in BIT;     -- start
    mode : in BIT_VECTOR(1 DOWNTO 0);   -- mode
    ecb : out BIT;      -- ecb
    cbc : out BIT;      -- cbc
    cfb : out BIT;      -- cfb
    ofb : out BIT;      -- ofb
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT ecb
    port (
    active : in BIT;    -- active
    clk : in BIT;       -- clk
    cke : in BIT;       -- cke
    key_ready : in BIT; -- key_ready
    finish : in BIT;    -- finish
    req_cp : in BIT;    -- req_cp
    e : in BIT; -- e
    e_mesin : out BIT;  -- e_mesin
    s_mesin : out BIT;  -- s_mesin
    s_gen_key : out BIT;        -- s_gen_key
    emp_buf : out BIT;  -- emp_buf
    cp_ready : out BIT; -- cp_ready
    cke_b_mode : out BIT;       -- cke_b_mode
    en_in : out BIT;    -- en_in
    en_iv : out BIT;    -- en_iv
    en_rcbc : out BIT;  -- en_rcbc
    en_out : out BIT;   -- en_out
    sel1 : out BIT_VECTOR(1 DOWNTO 0);  -- sel1
    sel2 : out BIT_VECTOR(1 DOWNTO 0);  -- sel2
    sel3 : out BIT_VECTOR(1 DOWNTO 0);  -- sel3
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT cbc
    port (
    active : in BIT;    -- active
    clk : in BIT;       -- clk
    cke : in BIT;       -- cke
    ikey_ready : in BIT;        -- ikey_ready
    key_ready : in BIT; -- key_ready
    dt_ready : in BIT;  -- dt_ready
    finish : in BIT;    -- finish
    e : in BIT; -- e
    first_dt : inout BIT;       -- first_dt
    e_mesin : out BIT;  -- e_mesin
    s_mesin : out BIT;  -- s_mesin
    s_gen_key : out BIT;        -- s_gen_key
    emp_buf : inout BIT;        -- emp_buf
    cp_ready : out BIT; -- cp_ready
    cke_b_mode : out BIT;       -- cke_b_mode
    en_in : out BIT;    -- en_in
    en_iv : out BIT;    -- en_iv
    en_rcbc : out BIT;  -- en_rcbc
    en_out : out BIT;   -- en_out
    sel1 : out BIT_VECTOR(1 DOWNTO 0);  -- sel1
    sel2 : out BIT_VECTOR(1 DOWNTO 0);  -- sel2
    sel3 : out BIT_VECTOR(1 DOWNTO 0);  -- sel3
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT cfb
    port (
    active : in BIT;    -- active
    clk : in BIT;       -- clk
    key_ready : in BIT; -- key_ready
    dt_ready : in BIT;  -- dt_ready
    finish : in BIT;    -- finish
    e : in BIT; -- e
    first_dt : inout BIT;       -- first_dt
    e_mesin : out BIT;  -- e_mesin
    s_mesin : out BIT;  -- s_mesin
    s_gen_key : out BIT;        -- s_gen_key
    emp_buf : out BIT;  -- emp_buf
    cp_ready : out BIT; -- cp_ready
    cke_b_mode : out BIT;       -- cke_b_mode
    en_in : out BIT;    -- en_in
    en_iv : out BIT;    -- en_iv
    en_rcbc : out BIT;  -- en_rcbc
    en_out : out BIT;   -- en_out
    sel1 : out BIT_VECTOR(1 DOWNTO 0);  -- sel1
    sel2 : out BIT_VECTOR(1 DOWNTO 0);  -- sel2
    sel3 : out BIT_VECTOR(1 DOWNTO 0);  -- sel3
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT ofb
    port (
    active : in BIT;    -- active
    clk : in BIT;       -- clk
    key_ready : in BIT; -- key_ready
    dt_ready : in BIT;  -- dt_ready
    finish : in BIT;    -- finish
    first_dt : inout BIT;       -- first_dt
    e_mesin : out BIT;  -- e_mesin
    s_mesin : out BIT;  -- s_mesin
    emp_buf : inout BIT;        -- emp_buf
    cp_ready : out BIT; -- cp_ready
    cke_b_mode : inout BIT;     -- cke_b_mode
    en_in : out BIT;    -- en_in
    en_iv : out BIT;    -- en_iv
    en_rcbc : out BIT;  -- en_rcbc
    en_out : out BIT;   -- en_out
    sel1 : out BIT_VECTOR(1 DOWNTO 0);  -- sel1
    sel2 : out BIT_VECTOR(1 DOWNTO 0);  -- sel2
    sel3 : out BIT_VECTOR(1 DOWNTO 0);  -- sel3
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT zero_x0
    port (
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT mux01
    port (
    a : in BIT; -- a
    b : in BIT; -- b
    c : in BIT; -- c
    d : in BIT; -- d
    sel : in BIT_VECTOR(1 DOWNTO 0);    -- sel
    o : out BIT;        -- o
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  COMPONENT mux02
    port (
    a : in BIT_VECTOR(1 DOWNTO 0);      -- a
    b : in BIT_VECTOR(1 DOWNTO 0);      -- b
    c : in BIT_VECTOR(1 DOWNTO 0);      -- c
    d : in BIT_VECTOR(1 DOWNTO 0);      -- d
    sel : in BIT_VECTOR(1 DOWNTO 0);    -- sel
    o : out BIT_VECTOR(1 DOWNTO 0);     -- o
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;
 
  SIGNAL cke_b_mode_cbc : BIT;  -- cke_b_mode_cbc
  SIGNAL cke_b_mode_cfb : BIT;  -- cke_b_mode_cfb
  SIGNAL cke_b_mode_ecb : BIT;  -- cke_b_mode_ecb
  SIGNAL cke_b_mode_ofb : BIT;  -- cke_b_mode_ofb
  SIGNAL cp_ready_cbc : BIT;    -- cp_ready_cbc
  SIGNAL cp_ready_cfb : BIT;    -- cp_ready_cfb
  SIGNAL cp_ready_ecb : BIT;    -- cp_ready_ecb
  SIGNAL cp_ready_ofb : BIT;    -- cp_ready_ofb
  SIGNAL e_mesin_cbc : BIT;     -- e_mesin_cbc
  SIGNAL e_mesin_cfb : BIT;     -- e_mesin_cfb
  SIGNAL e_mesin_ecb : BIT;     -- e_mesin_ecb
  SIGNAL e_mesin_ofb : BIT;     -- e_mesin_ofb
  SIGNAL emp_buf_cbc : BIT;     -- emp_buf_cbc
  SIGNAL emp_buf_cfb : BIT;     -- emp_buf_cfb
  SIGNAL emp_buf_ecb : BIT;     -- emp_buf_ecb
  SIGNAL emp_buf_ofb : BIT;     -- emp_buf_ofb
  SIGNAL en_in_cbc : BIT;       -- en_in_cbc
  SIGNAL en_in_cfb : BIT;       -- en_in_cfb
  SIGNAL en_in_ecb : BIT;       -- en_in_ecb
  SIGNAL en_in_ofb : BIT;       -- en_in_ofb
  SIGNAL en_iv_cbc : BIT;       -- en_iv_cbc
  SIGNAL en_iv_cfb : BIT;       -- en_iv_cfb
  SIGNAL en_iv_ecb : BIT;       -- en_iv_ecb
  SIGNAL en_iv_ofb : BIT;       -- en_iv_ofb
  SIGNAL en_out_cbc : BIT;      -- en_out_cbc
  SIGNAL en_out_cfb : BIT;      -- en_out_cfb
  SIGNAL en_out_ecb : BIT;      -- en_out_ecb
  SIGNAL en_out_ofb : BIT;      -- en_out_ofb
  SIGNAL en_rcbc_cbc : BIT;     -- en_rcbc_cbc
  SIGNAL en_rcbc_cfb : BIT;     -- en_rcbc_cfb
  SIGNAL en_rcbc_ecb : BIT;     -- en_rcbc_ecb
  SIGNAL en_rcbc_ofb : BIT;     -- en_rcbc_ofb
  SIGNAL first_dt_cbc : BIT;    -- first_dt_cbc
  SIGNAL first_dt_cfb : BIT;    -- first_dt_cfb
  SIGNAL first_dt_ofb : BIT;    -- first_dt_ofb
  SIGNAL modecbc : BIT; -- modecbc
  SIGNAL modecfb : BIT; -- modecfb
  SIGNAL modeecb : BIT; -- modeecb
  SIGNAL modeofb : BIT; -- modeofb
  SIGNAL nol : BIT;     -- nol
  SIGNAL s_gen_key_cbc : BIT;   -- s_gen_key_cbc
  SIGNAL s_gen_key_cfb : BIT;   -- s_gen_key_cfb
  SIGNAL s_gen_key_ecb : BIT;   -- s_gen_key_ecb
  SIGNAL s_mesin_cbc : BIT;     -- s_mesin_cbc
  SIGNAL s_mesin_cfb : BIT;     -- s_mesin_cfb
  SIGNAL s_mesin_ecb : BIT;     -- s_mesin_ecb
  SIGNAL s_mesin_ofb : BIT;     -- s_mesin_ofb
  SIGNAL sel1_cbc_0 : BIT;      -- sel1_cbc 0
  SIGNAL sel1_cbc_1 : BIT;      -- sel1_cbc 1
  SIGNAL sel1_cfb_0 : BIT;      -- sel1_cfb 0
  SIGNAL sel1_cfb_1 : BIT;      -- sel1_cfb 1
  SIGNAL sel1_ecb_0 : BIT;      -- sel1_ecb 0
  SIGNAL sel1_ecb_1 : BIT;      -- sel1_ecb 1
  SIGNAL sel1_ofb_0 : BIT;      -- sel1_ofb 0
  SIGNAL sel1_ofb_1 : BIT;      -- sel1_ofb 1
  SIGNAL sel2_cbc_0 : BIT;      -- sel2_cbc 0
  SIGNAL sel2_cbc_1 : BIT;      -- sel2_cbc 1
  SIGNAL sel2_cfb_0 : BIT;      -- sel2_cfb 0
  SIGNAL sel2_cfb_1 : BIT;      -- sel2_cfb 1
  SIGNAL sel2_ecb_0 : BIT;      -- sel2_ecb 0
  SIGNAL sel2_ecb_1 : BIT;      -- sel2_ecb 1
  SIGNAL sel2_ofb_0 : BIT;      -- sel2_ofb 0
  SIGNAL sel2_ofb_1 : BIT;      -- sel2_ofb 1
  SIGNAL sel3_cbc_0 : BIT;      -- sel3_cbc 0
  SIGNAL sel3_cbc_1 : BIT;      -- sel3_cbc 1
  SIGNAL sel3_cfb_0 : BIT;      -- sel3_cfb 0
  SIGNAL sel3_cfb_1 : BIT;      -- sel3_cfb 1
  SIGNAL sel3_ecb_0 : BIT;      -- sel3_ecb 0
  SIGNAL sel3_ecb_1 : BIT;      -- sel3_ecb 1
  SIGNAL sel3_ofb_0 : BIT;      -- sel3_ofb 0
  SIGNAL sel3_ofb_1 : BIT;      -- sel3_ofb 1
 
BEGIN
 
  decmode : dec_mode
    PORT MAP (
    vss => vss,
    vdd => vdd,
    ofb => modeofb,
    cfb => modecfb,
    cbc => modecbc,
    ecb => modeecb,
    mode => mode(1)& mode(0),
    start => start);
  ecb : ecb
    PORT MAP (
    vss => vss,
    vdd => vdd,
    sel3 => sel3_ecb_1& sel3_ecb_0,
    sel2 => sel2_ecb_1& sel2_ecb_0,
    sel1 => sel1_ecb_1& sel1_ecb_0,
    en_out => en_out_ecb,
    en_rcbc => en_rcbc_ecb,
    en_iv => en_iv_ecb,
    en_in => en_in_ecb,
    cke_b_mode => cke_b_mode_ecb,
    cp_ready => cp_ready_ecb,
    emp_buf => emp_buf_ecb,
    s_gen_key => s_gen_key_ecb,
    s_mesin => s_mesin_ecb,
    e_mesin => e_mesin_ecb,
    e => e,
    req_cp => req_cp,
    finish => finish,
    key_ready => key_ready,
    cke => cke,
    clk => clk,
    active => modeecb);
  cbc : cbc
    PORT MAP (
    vss => vss,
    vdd => vdd,
    sel3 => sel3_cbc_1& sel3_cbc_0,
    sel2 => sel2_cbc_1& sel2_cbc_0,
    sel1 => sel1_cbc_1& sel1_cbc_0,
    en_out => en_out_cbc,
    en_rcbc => en_rcbc_cbc,
    en_iv => en_iv_cbc,
    en_in => en_in_cbc,
    cke_b_mode => cke_b_mode_cbc,
    cp_ready => cp_ready_cbc,
    emp_buf => emp_buf_cbc,
    s_gen_key => s_gen_key_cbc,
    s_mesin => s_mesin_cbc,
    e_mesin => e_mesin_cbc,
    first_dt => first_dt_cbc,
    e => e,
    finish => finish,
    dt_ready => dt_ready,
    key_ready => key_ready,
    ikey_ready => ikey_ready,
    cke => cke,
    clk => clk,
    active => modecbc);
  cfb : cfb
    PORT MAP (
    vss => vss,
    vdd => vdd,
    sel3 => sel3_cfb_1& sel3_cfb_0,
    sel2 => sel2_cfb_1& sel2_cfb_0,
    sel1 => sel1_cfb_1& sel1_cfb_0,
    en_out => en_out_cfb,
    en_rcbc => en_rcbc_cfb,
    en_iv => en_iv_cfb,
    en_in => en_in_cfb,
    cke_b_mode => cke_b_mode_cfb,
    cp_ready => cp_ready_cfb,
    emp_buf => emp_buf_cfb,
    s_gen_key => s_gen_key_cfb,
    s_mesin => s_mesin_cfb,
    e_mesin => e_mesin_cfb,
    first_dt => first_dt_cfb,
    e => e,
    finish => finish,
    dt_ready => dt_ready,
    key_ready => key_ready,
    clk => clk,
    active => modecfb);
  ofb : ofb
    PORT MAP (
    vss => vss,
    vdd => vdd,
    sel3 => sel3_ofb_1& sel3_ofb_0,
    sel2 => sel2_ofb_1& sel2_ofb_0,
    sel1 => sel1_ofb_1& sel1_ofb_0,
    en_out => en_out_ofb,
    en_rcbc => en_rcbc_ofb,
    en_iv => en_iv_ofb,
    en_in => en_in_ofb,
    cke_b_mode => cke_b_mode_ofb,
    cp_ready => cp_ready_ofb,
    emp_buf => emp_buf_ofb,
    s_mesin => s_mesin_ofb,
    e_mesin => e_mesin_ofb,
    first_dt => first_dt_ofb,
    finish => finish,
    dt_ready => dt_ready,
    key_ready => key_ready,
    clk => clk,
    active => modeofb);
  zero : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => nol);
  mux_first_dt : mux01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => first_dt,
    sel => mode(1)& mode(0),
    d => first_dt_ofb,
    c => first_dt_cfb,
    b => first_dt_cbc,
    a => nol);
  mux_e_mesin : mux01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => e_mesin,
    sel => mode(1)& mode(0),
    d => e_mesin_ofb,
    c => e_mesin_cfb,
    b => e_mesin_cbc,
    a => e_mesin_ecb);
  mux_s_mesin : mux01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => s_mesin,
    sel => mode(1)& mode(0),
    d => s_mesin_ofb,
    c => s_mesin_cfb,
    b => s_mesin_cbc,
    a => s_mesin_ecb);
  mux_s_gen_key : mux01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => s_gen_key,
    sel => mode(1)& mode(0),
    d => cke_b_mode_ofb,
    c => s_gen_key_cfb,
    b => s_gen_key_cbc,
    a => s_gen_key_ecb);
  mux_emp_buf : mux01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => emp_buf,
    sel => mode(1)& mode(0),
    d => emp_buf_ofb,
    c => emp_buf_cfb,
    b => emp_buf_cbc,
    a => emp_buf_ecb);
  mux_cp_ready : mux01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => cp_ready,
    sel => mode(1)& mode(0),
    d => cp_ready_ofb,
    c => cp_ready_cfb,
    b => cp_ready_cbc,
    a => cp_ready_ecb);
  mux_cke_b_mode : mux01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => cke_b_mode,
    sel => mode(1)& mode(0),
    d => cke_b_mode_ofb,
    c => cke_b_mode_cfb,
    b => cke_b_mode_cbc,
    a => cke_b_mode_ecb);
  mux_en_in : mux01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => en_in,
    sel => mode(1)& mode(0),
    d => en_in_ofb,
    c => en_in_cfb,
    b => en_in_cbc,
    a => en_in_ecb);
  mux_en_iv : mux01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => en_iv,
    sel => mode(1)& mode(0),
    d => en_iv_ofb,
    c => en_iv_cfb,
    b => en_iv_cbc,
    a => en_iv_ecb);
  mux_en_rcbc : mux01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => en_rcbc,
    sel => mode(1)& mode(0),
    d => en_rcbc_ofb,
    c => en_rcbc_cfb,
    b => en_rcbc_cbc,
    a => en_rcbc_ecb);
  mux_en_out : mux01
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => en_out,
    sel => mode(1)& mode(0),
    d => en_out_ofb,
    c => en_out_cfb,
    b => en_out_cbc,
    a => en_out_ecb);
  mux_sel1 : mux02
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => sel1(1)& sel1(0),
    sel => mode(1)& mode(0),
    d => sel1_ofb_1& sel1_ofb_0,
    c => sel1_cfb_1& sel1_cfb_0,
    b => sel1_cbc_1& sel1_cbc_0,
    a => sel1_ecb_1& sel1_ecb_0);
  mux_sel2 : mux02
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => sel2(1)& sel2(0),
    sel => mode(1)& mode(0),
    d => sel2_ofb_1& sel2_ofb_0,
    c => sel2_cfb_1& sel2_cfb_0,
    b => sel2_cbc_1& sel2_cbc_0,
    a => sel2_ecb_1& sel2_ecb_0);
  mux_sel3 : mux02
    PORT MAP (
    vss => vss,
    vdd => vdd,
    o => sel3(1)& sel3(0),
    sel => mode(1)& mode(0),
    d => sel3_ofb_1& sel3_ofb_0,
    c => sel3_cfb_1& sel3_cfb_0,
    b => sel3_cbc_1& sel3_cbc_0,
    a => sel3_ecb_1& sel3_ecb_0);
 
end VST;

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[/] [structural_vhdl/] [tags/] [vlsi/] [main control/] [controlmode.vst] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	marta	-- VHDL structural description generated from `controlmode`
2			`-- date : Sat Sep 1 20:27:01 2001`
3
4
5			`-- Entity Declaration`
6
7			`ENTITY controlmode IS`
8			`PORT (`
9			`clk : in BIT; -- clk`
10			`start : in BIT; -- start`
11			`mode : in BIT_VECTOR (0 TO 1); -- mode`
12			`cke : in BIT; -- cke`
13			`ikey_ready : in BIT; -- ikey_ready`
14			`key_ready : in BIT; -- key_ready`
15			`dt_ready : in BIT; -- dt_ready`
16			`finish : in BIT; -- finish`
17			`req_cp : in BIT; -- req_cp`
18			`e : in BIT; -- e`
19			`first_dt : out BIT; -- first_dt`
20			`e_mesin : out BIT; -- e_mesin`
21			`s_mesin : out BIT; -- s_mesin`
22			`s_gen_key : out BIT; -- s_gen_key`
23			`emp_buf : out BIT; -- emp_buf`
24			`cp_ready : out BIT; -- cp_ready`
25			`cke_b_mode : out BIT; -- cke_b_mode`
26			`en_in : out BIT; -- en_in`
27			`en_iv : out BIT; -- en_iv`
28			`en_rcbc : out BIT; -- en_rcbc`
29			`en_out : out BIT; -- en_out`
30			`sel1 : out BIT_VECTOR (0 TO 1); -- sel1`
31			`sel2 : out BIT_VECTOR (0 TO 1); -- sel2`
32			`sel3 : out BIT_VECTOR (0 TO 1); -- sel3`
33			`vdd : in BIT; -- vdd`
34			`vss : in BIT -- vss`
35			`);`
36			`END controlmode;`
37
38			`-- Architecture Declaration`
39
40			`ARCHITECTURE VST OF controlmode IS`
41			`COMPONENT dec_mode`
42			`port (`
43			`start : in BIT; -- start`
44			`mode : in BIT_VECTOR(1 DOWNTO 0); -- mode`
45			`ecb : out BIT; -- ecb`
46			`cbc : out BIT; -- cbc`
47			`cfb : out BIT; -- cfb`
48			`ofb : out BIT; -- ofb`
49			`vdd : in BIT; -- vdd`
50			`vss : in BIT -- vss`
51			`);`
52			`END COMPONENT;`
53
54			`COMPONENT ecb`
55			`port (`
56			`active : in BIT; -- active`
57			`clk : in BIT; -- clk`
58			`cke : in BIT; -- cke`
59			`key_ready : in BIT; -- key_ready`
60			`finish : in BIT; -- finish`
61			`req_cp : in BIT; -- req_cp`
62			`e : in BIT; -- e`
63			`e_mesin : out BIT; -- e_mesin`
64			`s_mesin : out BIT; -- s_mesin`
65			`s_gen_key : out BIT; -- s_gen_key`
66			`emp_buf : out BIT; -- emp_buf`
67			`cp_ready : out BIT; -- cp_ready`
68			`cke_b_mode : out BIT; -- cke_b_mode`
69			`en_in : out BIT; -- en_in`
70			`en_iv : out BIT; -- en_iv`
71			`en_rcbc : out BIT; -- en_rcbc`
72			`en_out : out BIT; -- en_out`
73			`sel1 : out BIT_VECTOR(1 DOWNTO 0); -- sel1`
74			`sel2 : out BIT_VECTOR(1 DOWNTO 0); -- sel2`
75			`sel3 : out BIT_VECTOR(1 DOWNTO 0); -- sel3`
76			`vdd : in BIT; -- vdd`
77			`vss : in BIT -- vss`
78			`);`
79			`END COMPONENT;`
80
81			`COMPONENT cbc`
82			`port (`
83			`active : in BIT; -- active`
84			`clk : in BIT; -- clk`
85			`cke : in BIT; -- cke`
86			`ikey_ready : in BIT; -- ikey_ready`
87			`key_ready : in BIT; -- key_ready`
88			`dt_ready : in BIT; -- dt_ready`
89			`finish : in BIT; -- finish`
90			`e : in BIT; -- e`
91			`first_dt : inout BIT; -- first_dt`
92			`e_mesin : out BIT; -- e_mesin`
93			`s_mesin : out BIT; -- s_mesin`
94			`s_gen_key : out BIT; -- s_gen_key`
95			`emp_buf : inout BIT; -- emp_buf`
96			`cp_ready : out BIT; -- cp_ready`
97			`cke_b_mode : out BIT; -- cke_b_mode`
98			`en_in : out BIT; -- en_in`
99			`en_iv : out BIT; -- en_iv`
100			`en_rcbc : out BIT; -- en_rcbc`
101			`en_out : out BIT; -- en_out`
102			`sel1 : out BIT_VECTOR(1 DOWNTO 0); -- sel1`
103			`sel2 : out BIT_VECTOR(1 DOWNTO 0); -- sel2`
104			`sel3 : out BIT_VECTOR(1 DOWNTO 0); -- sel3`
105			`vdd : in BIT; -- vdd`
106			`vss : in BIT -- vss`
107			`);`
108			`END COMPONENT;`
109
110			`COMPONENT cfb`
111			`port (`
112			`active : in BIT; -- active`
113			`clk : in BIT; -- clk`
114			`key_ready : in BIT; -- key_ready`
115			`dt_ready : in BIT; -- dt_ready`
116			`finish : in BIT; -- finish`
117			`e : in BIT; -- e`
118			`first_dt : inout BIT; -- first_dt`
119			`e_mesin : out BIT; -- e_mesin`
120			`s_mesin : out BIT; -- s_mesin`
121			`s_gen_key : out BIT; -- s_gen_key`
122			`emp_buf : out BIT; -- emp_buf`
123			`cp_ready : out BIT; -- cp_ready`
124			`cke_b_mode : out BIT; -- cke_b_mode`
125			`en_in : out BIT; -- en_in`
126			`en_iv : out BIT; -- en_iv`
127			`en_rcbc : out BIT; -- en_rcbc`
128			`en_out : out BIT; -- en_out`
129			`sel1 : out BIT_VECTOR(1 DOWNTO 0); -- sel1`
130			`sel2 : out BIT_VECTOR(1 DOWNTO 0); -- sel2`
131			`sel3 : out BIT_VECTOR(1 DOWNTO 0); -- sel3`
132			`vdd : in BIT; -- vdd`
133			`vss : in BIT -- vss`
134			`);`
135			`END COMPONENT;`
136
137			`COMPONENT ofb`
138			`port (`
139			`active : in BIT; -- active`
140			`clk : in BIT; -- clk`
141			`key_ready : in BIT; -- key_ready`
142			`dt_ready : in BIT; -- dt_ready`
143			`finish : in BIT; -- finish`
144			`first_dt : inout BIT; -- first_dt`
145			`e_mesin : out BIT; -- e_mesin`
146			`s_mesin : out BIT; -- s_mesin`
147			`emp_buf : inout BIT; -- emp_buf`
148			`cp_ready : out BIT; -- cp_ready`
149			`cke_b_mode : inout BIT; -- cke_b_mode`
150			`en_in : out BIT; -- en_in`
151			`en_iv : out BIT; -- en_iv`
152			`en_rcbc : out BIT; -- en_rcbc`
153			`en_out : out BIT; -- en_out`
154			`sel1 : out BIT_VECTOR(1 DOWNTO 0); -- sel1`
155			`sel2 : out BIT_VECTOR(1 DOWNTO 0); -- sel2`
156			`sel3 : out BIT_VECTOR(1 DOWNTO 0); -- sel3`
157			`vdd : in BIT; -- vdd`
158			`vss : in BIT -- vss`
159			`);`
160			`END COMPONENT;`
161
162			`COMPONENT zero_x0`
163			`port (`
164			`nq : out BIT; -- nq`
165			`vdd : in BIT; -- vdd`
166			`vss : in BIT -- vss`
167			`);`
168			`END COMPONENT;`
169
170			`COMPONENT mux01`
171			`port (`
172			`a : in BIT; -- a`
173			`b : in BIT; -- b`
174			`c : in BIT; -- c`
175			`d : in BIT; -- d`
176			`sel : in BIT_VECTOR(1 DOWNTO 0); -- sel`
177			`o : out BIT; -- o`
178			`vdd : in BIT; -- vdd`
179			`vss : in BIT -- vss`
180			`);`
181			`END COMPONENT;`
182
183			`COMPONENT mux02`
184			`port (`
185			`a : in BIT_VECTOR(1 DOWNTO 0); -- a`
186			`b : in BIT_VECTOR(1 DOWNTO 0); -- b`
187			`c : in BIT_VECTOR(1 DOWNTO 0); -- c`
188			`d : in BIT_VECTOR(1 DOWNTO 0); -- d`
189			`sel : in BIT_VECTOR(1 DOWNTO 0); -- sel`
190			`o : out BIT_VECTOR(1 DOWNTO 0); -- o`
191			`vdd : in BIT; -- vdd`
192			`vss : in BIT -- vss`
193			`);`
194			`END COMPONENT;`
195
196			`SIGNAL cke_b_mode_cbc : BIT; -- cke_b_mode_cbc`
197			`SIGNAL cke_b_mode_cfb : BIT; -- cke_b_mode_cfb`
198			`SIGNAL cke_b_mode_ecb : BIT; -- cke_b_mode_ecb`
199			`SIGNAL cke_b_mode_ofb : BIT; -- cke_b_mode_ofb`
200			`SIGNAL cp_ready_cbc : BIT; -- cp_ready_cbc`
201			`SIGNAL cp_ready_cfb : BIT; -- cp_ready_cfb`
202			`SIGNAL cp_ready_ecb : BIT; -- cp_ready_ecb`
203			`SIGNAL cp_ready_ofb : BIT; -- cp_ready_ofb`
204			`SIGNAL e_mesin_cbc : BIT; -- e_mesin_cbc`
205			`SIGNAL e_mesin_cfb : BIT; -- e_mesin_cfb`
206			`SIGNAL e_mesin_ecb : BIT; -- e_mesin_ecb`
207			`SIGNAL e_mesin_ofb : BIT; -- e_mesin_ofb`
208			`SIGNAL emp_buf_cbc : BIT; -- emp_buf_cbc`
209			`SIGNAL emp_buf_cfb : BIT; -- emp_buf_cfb`
210			`SIGNAL emp_buf_ecb : BIT; -- emp_buf_ecb`
211			`SIGNAL emp_buf_ofb : BIT; -- emp_buf_ofb`
212			`SIGNAL en_in_cbc : BIT; -- en_in_cbc`
213			`SIGNAL en_in_cfb : BIT; -- en_in_cfb`
214			`SIGNAL en_in_ecb : BIT; -- en_in_ecb`
215			`SIGNAL en_in_ofb : BIT; -- en_in_ofb`
216			`SIGNAL en_iv_cbc : BIT; -- en_iv_cbc`
217			`SIGNAL en_iv_cfb : BIT; -- en_iv_cfb`
218			`SIGNAL en_iv_ecb : BIT; -- en_iv_ecb`
219			`SIGNAL en_iv_ofb : BIT; -- en_iv_ofb`
220			`SIGNAL en_out_cbc : BIT; -- en_out_cbc`
221			`SIGNAL en_out_cfb : BIT; -- en_out_cfb`
222			`SIGNAL en_out_ecb : BIT; -- en_out_ecb`
223			`SIGNAL en_out_ofb : BIT; -- en_out_ofb`
224			`SIGNAL en_rcbc_cbc : BIT; -- en_rcbc_cbc`
225			`SIGNAL en_rcbc_cfb : BIT; -- en_rcbc_cfb`
226			`SIGNAL en_rcbc_ecb : BIT; -- en_rcbc_ecb`
227			`SIGNAL en_rcbc_ofb : BIT; -- en_rcbc_ofb`
228			`SIGNAL first_dt_cbc : BIT; -- first_dt_cbc`
229			`SIGNAL first_dt_cfb : BIT; -- first_dt_cfb`
230			`SIGNAL first_dt_ofb : BIT; -- first_dt_ofb`
231			`SIGNAL modecbc : BIT; -- modecbc`
232			`SIGNAL modecfb : BIT; -- modecfb`
233			`SIGNAL modeecb : BIT; -- modeecb`
234			`SIGNAL modeofb : BIT; -- modeofb`
235			`SIGNAL nol : BIT; -- nol`
236			`SIGNAL s_gen_key_cbc : BIT; -- s_gen_key_cbc`
237			`SIGNAL s_gen_key_cfb : BIT; -- s_gen_key_cfb`
238			`SIGNAL s_gen_key_ecb : BIT; -- s_gen_key_ecb`
239			`SIGNAL s_mesin_cbc : BIT; -- s_mesin_cbc`
240			`SIGNAL s_mesin_cfb : BIT; -- s_mesin_cfb`
241			`SIGNAL s_mesin_ecb : BIT; -- s_mesin_ecb`
242			`SIGNAL s_mesin_ofb : BIT; -- s_mesin_ofb`
243			`SIGNAL sel1_cbc_0 : BIT; -- sel1_cbc 0`
244			`SIGNAL sel1_cbc_1 : BIT; -- sel1_cbc 1`
245			`SIGNAL sel1_cfb_0 : BIT; -- sel1_cfb 0`
246			`SIGNAL sel1_cfb_1 : BIT; -- sel1_cfb 1`
247			`SIGNAL sel1_ecb_0 : BIT; -- sel1_ecb 0`
248			`SIGNAL sel1_ecb_1 : BIT; -- sel1_ecb 1`
249			`SIGNAL sel1_ofb_0 : BIT; -- sel1_ofb 0`
250			`SIGNAL sel1_ofb_1 : BIT; -- sel1_ofb 1`
251			`SIGNAL sel2_cbc_0 : BIT; -- sel2_cbc 0`
252			`SIGNAL sel2_cbc_1 : BIT; -- sel2_cbc 1`
253			`SIGNAL sel2_cfb_0 : BIT; -- sel2_cfb 0`
254			`SIGNAL sel2_cfb_1 : BIT; -- sel2_cfb 1`
255			`SIGNAL sel2_ecb_0 : BIT; -- sel2_ecb 0`
256			`SIGNAL sel2_ecb_1 : BIT; -- sel2_ecb 1`
257			`SIGNAL sel2_ofb_0 : BIT; -- sel2_ofb 0`
258			`SIGNAL sel2_ofb_1 : BIT; -- sel2_ofb 1`
259			`SIGNAL sel3_cbc_0 : BIT; -- sel3_cbc 0`
260			`SIGNAL sel3_cbc_1 : BIT; -- sel3_cbc 1`
261			`SIGNAL sel3_cfb_0 : BIT; -- sel3_cfb 0`
262			`SIGNAL sel3_cfb_1 : BIT; -- sel3_cfb 1`
263			`SIGNAL sel3_ecb_0 : BIT; -- sel3_ecb 0`
264			`SIGNAL sel3_ecb_1 : BIT; -- sel3_ecb 1`
265			`SIGNAL sel3_ofb_0 : BIT; -- sel3_ofb 0`
266			`SIGNAL sel3_ofb_1 : BIT; -- sel3_ofb 1`
267
268			`BEGIN`
269
270			`decmode : dec_mode`
271			`PORT MAP (`
272			`vss => vss,`
273			`vdd => vdd,`
274			`ofb => modeofb,`
275			`cfb => modecfb,`
276			`cbc => modecbc,`
277			`ecb => modeecb,`
278			`mode => mode(1)& mode(0),`
279			`start => start);`
280			`ecb : ecb`
281			`PORT MAP (`
282			`vss => vss,`
283			`vdd => vdd,`
284			`sel3 => sel3_ecb_1& sel3_ecb_0,`
285			`sel2 => sel2_ecb_1& sel2_ecb_0,`
286			`sel1 => sel1_ecb_1& sel1_ecb_0,`
287			`en_out => en_out_ecb,`
288			`en_rcbc => en_rcbc_ecb,`
289			`en_iv => en_iv_ecb,`
290			`en_in => en_in_ecb,`
291			`cke_b_mode => cke_b_mode_ecb,`
292			`cp_ready => cp_ready_ecb,`
293			`emp_buf => emp_buf_ecb,`
294			`s_gen_key => s_gen_key_ecb,`
295			`s_mesin => s_mesin_ecb,`
296			`e_mesin => e_mesin_ecb,`
297			`e => e,`
298			`req_cp => req_cp,`
299			`finish => finish,`
300			`key_ready => key_ready,`
301			`cke => cke,`
302			`clk => clk,`
303			`active => modeecb);`
304			`cbc : cbc`
305			`PORT MAP (`
306			`vss => vss,`
307			`vdd => vdd,`
308			`sel3 => sel3_cbc_1& sel3_cbc_0,`
309			`sel2 => sel2_cbc_1& sel2_cbc_0,`
310			`sel1 => sel1_cbc_1& sel1_cbc_0,`
311			`en_out => en_out_cbc,`
312			`en_rcbc => en_rcbc_cbc,`
313			`en_iv => en_iv_cbc,`
314			`en_in => en_in_cbc,`
315			`cke_b_mode => cke_b_mode_cbc,`
316			`cp_ready => cp_ready_cbc,`
317			`emp_buf => emp_buf_cbc,`
318			`s_gen_key => s_gen_key_cbc,`
319			`s_mesin => s_mesin_cbc,`
320			`e_mesin => e_mesin_cbc,`
321			`first_dt => first_dt_cbc,`
322			`e => e,`
323			`finish => finish,`
324			`dt_ready => dt_ready,`
325			`key_ready => key_ready,`
326			`ikey_ready => ikey_ready,`
327			`cke => cke,`
328			`clk => clk,`
329			`active => modecbc);`
330			`cfb : cfb`
331			`PORT MAP (`
332			`vss => vss,`
333			`vdd => vdd,`
334			`sel3 => sel3_cfb_1& sel3_cfb_0,`
335			`sel2 => sel2_cfb_1& sel2_cfb_0,`
336			`sel1 => sel1_cfb_1& sel1_cfb_0,`
337			`en_out => en_out_cfb,`
338			`en_rcbc => en_rcbc_cfb,`
339			`en_iv => en_iv_cfb,`
340			`en_in => en_in_cfb,`
341			`cke_b_mode => cke_b_mode_cfb,`
342			`cp_ready => cp_ready_cfb,`
343			`emp_buf => emp_buf_cfb,`
344			`s_gen_key => s_gen_key_cfb,`
345			`s_mesin => s_mesin_cfb,`
346			`e_mesin => e_mesin_cfb,`
347			`first_dt => first_dt_cfb,`
348			`e => e,`
349			`finish => finish,`
350			`dt_ready => dt_ready,`
351			`key_ready => key_ready,`
352			`clk => clk,`
353			`active => modecfb);`
354			`ofb : ofb`
355			`PORT MAP (`
356			`vss => vss,`
357			`vdd => vdd,`
358			`sel3 => sel3_ofb_1& sel3_ofb_0,`
359			`sel2 => sel2_ofb_1& sel2_ofb_0,`
360			`sel1 => sel1_ofb_1& sel1_ofb_0,`
361			`en_out => en_out_ofb,`
362			`en_rcbc => en_rcbc_ofb,`
363			`en_iv => en_iv_ofb,`
364			`en_in => en_in_ofb,`
365			`cke_b_mode => cke_b_mode_ofb,`
366			`cp_ready => cp_ready_ofb,`
367			`emp_buf => emp_buf_ofb,`
368			`s_mesin => s_mesin_ofb,`
369			`e_mesin => e_mesin_ofb,`
370			`first_dt => first_dt_ofb,`
371			`finish => finish,`
372			`dt_ready => dt_ready,`
373			`key_ready => key_ready,`
374			`clk => clk,`
375			`active => modeofb);`
376			`zero : zero_x0`
377			`PORT MAP (`
378			`vss => vss,`
379			`vdd => vdd,`
380			`nq => nol);`
381			`mux_first_dt : mux01`
382			`PORT MAP (`
383			`vss => vss,`
384			`vdd => vdd,`
385			`o => first_dt,`
386			`sel => mode(1)& mode(0),`
387			`d => first_dt_ofb,`
388			`c => first_dt_cfb,`
389			`b => first_dt_cbc,`
390			`a => nol);`
391			`mux_e_mesin : mux01`
392			`PORT MAP (`
393			`vss => vss,`
394			`vdd => vdd,`
395			`o => e_mesin,`
396			`sel => mode(1)& mode(0),`
397			`d => e_mesin_ofb,`
398			`c => e_mesin_cfb,`
399			`b => e_mesin_cbc,`
400			`a => e_mesin_ecb);`
401			`mux_s_mesin : mux01`
402			`PORT MAP (`
403			`vss => vss,`
404			`vdd => vdd,`
405			`o => s_mesin,`
406			`sel => mode(1)& mode(0),`
407			`d => s_mesin_ofb,`
408			`c => s_mesin_cfb,`
409			`b => s_mesin_cbc,`
410			`a => s_mesin_ecb);`
411			`mux_s_gen_key : mux01`
412			`PORT MAP (`
413			`vss => vss,`
414			`vdd => vdd,`
415			`o => s_gen_key,`
416			`sel => mode(1)& mode(0),`
417			`d => cke_b_mode_ofb,`
418			`c => s_gen_key_cfb,`
419			`b => s_gen_key_cbc,`
420			`a => s_gen_key_ecb);`
421			`mux_emp_buf : mux01`
422			`PORT MAP (`
423			`vss => vss,`
424			`vdd => vdd,`
425			`o => emp_buf,`
426			`sel => mode(1)& mode(0),`
427			`d => emp_buf_ofb,`
428			`c => emp_buf_cfb,`
429			`b => emp_buf_cbc,`
430			`a => emp_buf_ecb);`
431			`mux_cp_ready : mux01`
432			`PORT MAP (`
433			`vss => vss,`
434			`vdd => vdd,`
435			`o => cp_ready,`
436			`sel => mode(1)& mode(0),`
437			`d => cp_ready_ofb,`
438			`c => cp_ready_cfb,`
439			`b => cp_ready_cbc,`
440			`a => cp_ready_ecb);`
441			`mux_cke_b_mode : mux01`
442			`PORT MAP (`
443			`vss => vss,`
444			`vdd => vdd,`
445			`o => cke_b_mode,`
446			`sel => mode(1)& mode(0),`
447			`d => cke_b_mode_ofb,`
448			`c => cke_b_mode_cfb,`
449			`b => cke_b_mode_cbc,`
450			`a => cke_b_mode_ecb);`
451			`mux_en_in : mux01`
452			`PORT MAP (`
453			`vss => vss,`
454			`vdd => vdd,`
455			`o => en_in,`
456			`sel => mode(1)& mode(0),`
457			`d => en_in_ofb,`
458			`c => en_in_cfb,`
459			`b => en_in_cbc,`
460			`a => en_in_ecb);`
461			`mux_en_iv : mux01`
462			`PORT MAP (`
463			`vss => vss,`
464			`vdd => vdd,`
465			`o => en_iv,`
466			`sel => mode(1)& mode(0),`
467			`d => en_iv_ofb,`
468			`c => en_iv_cfb,`
469			`b => en_iv_cbc,`
470			`a => en_iv_ecb);`
471			`mux_en_rcbc : mux01`
472			`PORT MAP (`
473			`vss => vss,`
474			`vdd => vdd,`
475			`o => en_rcbc,`
476			`sel => mode(1)& mode(0),`
477			`d => en_rcbc_ofb,`
478			`c => en_rcbc_cfb,`
479			`b => en_rcbc_cbc,`
480			`a => en_rcbc_ecb);`
481			`mux_en_out : mux01`
482			`PORT MAP (`
483			`vss => vss,`
484			`vdd => vdd,`
485			`o => en_out,`
486			`sel => mode(1)& mode(0),`
487			`d => en_out_ofb,`
488			`c => en_out_cfb,`
489			`b => en_out_cbc,`
490			`a => en_out_ecb);`
491			`mux_sel1 : mux02`
492			`PORT MAP (`
493			`vss => vss,`
494			`vdd => vdd,`
495			`o => sel1(1)& sel1(0),`
496			`sel => mode(1)& mode(0),`
497			`d => sel1_ofb_1& sel1_ofb_0,`
498			`c => sel1_cfb_1& sel1_cfb_0,`
499			`b => sel1_cbc_1& sel1_cbc_0,`
500			`a => sel1_ecb_1& sel1_ecb_0);`
501			`mux_sel2 : mux02`
502			`PORT MAP (`
503			`vss => vss,`
504			`vdd => vdd,`
505			`o => sel2(1)& sel2(0),`
506			`sel => mode(1)& mode(0),`
507			`d => sel2_ofb_1& sel2_ofb_0,`
508			`c => sel2_cfb_1& sel2_cfb_0,`
509			`b => sel2_cbc_1& sel2_cbc_0,`
510			`a => sel2_ecb_1& sel2_ecb_0);`
511			`mux_sel3 : mux02`
512			`PORT MAP (`
513			`vss => vss,`
514			`vdd => vdd,`
515			`o => sel3(1)& sel3(0),`
516			`sel => mode(1)& mode(0),`
517			`d => sel3_ofb_1& sel3_ofb_0,`
518			`c => sel3_cfb_1& sel3_cfb_0,`
519			`b => sel3_cbc_1& sel3_cbc_0,`
520			`a => sel3_ecb_1& sel3_ecb_0);`
521
522			`end VST;`