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[/] [structural_vhdl/] [tags/] [vlsi/] [main control/] [dec_mode.vst] - Blame information for rev 4

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1 2 marta 
-- VHDL structural description generated from `dec_mode`
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--              date : Sat Sep  1 20:26:07 2001
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-- Entity Declaration
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ENTITY dec_mode IS
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  PORT (
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  start : in BIT;       -- start
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  mode : in BIT_VECTOR (1 DOWNTO 0);    -- mode
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  ecb : out BIT;        -- ecb
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  cbc : out BIT;        -- cbc
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  cfb : out BIT;        -- cfb
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  ofb : out BIT;        -- ofb
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END dec_mode;
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-- Architecture Declaration
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ARCHITECTURE VST OF dec_mode IS
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  COMPONENT a2_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT a3_x2
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    i2 : in BIT;        -- i2
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT inv_x1
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    port (
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    i : in BIT; -- i
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    nq : out BIT;       -- nq
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  COMPONENT an12_x1
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    port (
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    i0 : in BIT;        -- i0
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    i1 : in BIT;        -- i1
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    q : out BIT;        -- q
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    vdd : in BIT;       -- vdd
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    vss : in BIT        -- vss
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    );
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  END COMPONENT;
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  SIGNAL auxsc3 : BIT;  -- auxsc3
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  SIGNAL auxsc6 : BIT;  -- auxsc6
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  SIGNAL auxsc7 : BIT;  -- auxsc7
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  SIGNAL auxsc8 : BIT;  -- auxsc8
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BEGIN
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  ofb : a3_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => ofb,
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    i2 => start,
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    i1 => mode(1),
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    i0 => mode(0));
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  cfb : a2_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => cfb,
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    i1 => auxsc3,
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    i0 => start);
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  cbc : a2_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => cbc,
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    i1 => auxsc6,
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    i0 => start);
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  ecb : a3_x2
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => ecb,
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    i2 => auxsc8,
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    i1 => auxsc7,
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    i0 => start);
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  auxsc8 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc8,
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    i => mode(1));
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  auxsc7 : inv_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    nq => auxsc7,
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    i => mode(0));
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  auxsc6 : an12_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc6,
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    i1 => mode(0),
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    i0 => mode(1));
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  auxsc3 : an12_x1
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    PORT MAP (
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    vss => vss,
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    vdd => vdd,
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    q => auxsc3,
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    i1 => mode(1),
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    i0 => mode(0));
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end VST;

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